Pulse Contributors Code frequency Recent commits

2025-12-16 - 2026-03-16

Period: 3 months

1 day 3 days 1 week 1 month 3 months 6 months 1 year

Overview

1 active pull request

6 active issues

1
Merged pull request 0
Proposed pull requests 6
Closed issues 0
New issues

Excluding merges, 1 author has pushed 2 commits to master and 2 commits to all branches. On master, 2 files have changed and there have been 91 additions and 21 deletions.

1 pull request merged by 1 user

Merged #24 nlnet-2024-12-324 amendment 1 2026-03-11 01:24:36 +00:00

6 issues closed from 1 user

Closed #22 NLnet 2024-12-324 Attempt Proof that our CPU but with zeroed outputs for all eventually-cancelled instructions is equivalent to our real CPU design 2026-03-11 01:27:37 +00:00

Closed #21 NLnet 2024-12-324 Write Rocq and HDL logic for tracking which instructions will eventually be cancelled and which will eventually be retired. 2026-03-11 01:27:17 +00:00

Closed #11 NLnet 2024-12-324 Create the fetch and i-cache logic. 2026-02-22 21:32:50 +00:00

Closed #12 NLnet 2024-12-324 Create the PowerISA decoder 2026-01-29 02:23:38 +00:00

Closed #10 NLnet 2024-12-324 Create the next-instruction logic 2025-12-17 07:55:08 +00:00

Closed #13 NLnet 2024-12-324 Create a model of the instruction fetch/decode control system, using procedural implementations of the most complex HDL modules where appropriate. 2025-12-17 07:55:08 +00:00

3 unresolved conversations

Open #3 NLnet 2024-12-324 Write the code to do the translation in Fayalite. 2026-03-11 01:27:09 +00:00

Open #15 NLnet 2024-12-324 memory system: main memory and IO devices 2026-03-02 21:21:42 +00:00

Open #8 NLnet 2024-12-324 Create a model of the whole rename/execute/retire control system, using procedural implementations of the most complex HDL modules where appropriate. 2026-02-23 19:39:17 +00:00