2026-02-06 - 2026-05-06
Overview
3 pull requests merged by 1 user
Merged
#26 Replace nlnet-2024-12-324/plan-amendment-1.txt with NLnet's new version since they decided to replace the amendment rather than create an new one
Merged
#25 add required skills to nlnet-2024-12-324/progress.md
Merged
#24 nlnet-2024-12-324 amendment 1
4 issues closed from 1 user
Closed
#15 NLnet 2024-12-324 memory system: main memory and IO devices
Closed
#22 NLnet 2024-12-324 Attempt Proof that our CPU but with zeroed outputs for all eventually-cancelled instructions is equivalent to our real CPU design
Closed
#21 NLnet 2024-12-324 Write Rocq and HDL logic for tracking which instructions will eventually be cancelled and which will eventually be retired.
Closed
#11 NLnet 2024-12-324 Create the fetch and i-cache logic.
11 unresolved conversations
Open
#8
NLnet 2024-12-324 Create a model of the whole rename/execute/retire control system, using procedural implementations of the most complex HDL modules where appropriate.
Open
#20
NLnet 2024-12-324 adding order-violation detection logic
Open
#19
NLnet 2024-12-324 adding atomics: lr/sc, atomic fetch-add (or other fetch-op)
Open
#18
NLnet 2024-12-324 memory store execution unit
Open
#17
NLnet 2024-12-324 memory load execution unit (we'll want to be able to do more than one load at once)
Open
#16
NLnet 2024-12-324 d-cache
Open
#14
NLnet 2024-12-324 Translate the procedural model to use actual synthesizeable HDL.
Open
#9
NLnet 2024-12-324 Translate the procedural model to use actual synthesizeable HDL
Open
#5
NLnet 2024-12-324 Add support for the Orange Crab since both Cesar and Jacob have one.
Open
#3
NLnet 2024-12-324 Write the code to do the translation in Fayalite.
Open
#2
NLnet 2024-12-324 Figure out how exactly we should represent HDL in Rocq