NLnet 2024-12-324 adding order-violation detection logic #20

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opened 2025-08-26 07:13:12 +00:00 by programmerjake · 0 comments

Issue for tracking progress of a subtask of NLnet grant 2024-12-324:
adding order-violation detection logic, so we can make memory look like it has total-store-order (for x86), or even sequential consistency (meaning we can ignore all non-IO fences)

Issue for tracking progress of a subtask of [NLnet grant 2024-12-324](https://git.libre-chip.org/libre-chip/grant-tracking/src/branch/master/nlnet-2024-12-324/progress.md): adding order-violation detection logic, so we can make memory look like it has total-store-order (for x86), or even sequential consistency (meaning we can ignore all non-IO fences) <!-- add additional content here if you like -->
programmerjake added this to the NLnet 2024-12-324 Libre-Chip's First CPU Architecture And Formal Proof of No Spectre bugs project 2025-08-26 07:13:12 +00:00
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Reference: libre-chip/grant-tracking#20
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