NLnet 2024-12-324 Translate the procedural model to use actual synthesizeable HDL #9
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Reference: libre-chip/grant-tracking#9
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Issue for tracking progress of a subtask of NLnet grant 2024-12-324:
Translate the procedural model to use actual synthesizeable HDL. includes a proof of correctness of the out-of-order CPU in relation to a sequential CPU (probably most easily done by adding the proof to the retire stage).