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NLnet 2024-12-324 Figure out how exactly we should represent HDL in Rocq #2

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opened 2025-08-26 02:28:40 +00:00 by programmerjake · 0 comments
programmerjake commented 2025-08-26 02:28:40 +00:00
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Issue for tracking progress of a subtask of NLnet grant 2024-12-324:
Figure out how exactly we should represent HDL in Rocq, writing down a manually-translated version of common HDL components (e.g. how to translate a register, a memory, an add/sub/mul/div, etc.).

Issue for tracking progress of a subtask of [NLnet grant 2024-12-324](https://git.libre-chip.org/libre-chip/grant-tracking/src/branch/master/nlnet-2024-12-324/progress.md): Figure out how exactly we should represent HDL in Rocq, writing down a manually-translated version of common HDL components (e.g. how to translate a register, a memory, an add/sub/mul/div, etc.). <!-- add additional content here if you like -->
programmerjake added this to the NLnet 2024-12-324 Libre-Chip's First CPU Architecture And Formal Proof of No Spectre bugs project 2025-08-26 02:28:40 +00:00
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NLnet 2024-12-324 Libre-Chip's First CPU Architecture And Formal Proof of No Spectre bugs
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#3 NLnet 2024-12-324 Write the code to do the translation in Fayalite.
libre-chip/grant-tracking
Reference: libre-chip/grant-tracking#2
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