NLnet 2024-12-324 Attempt Proof that our CPU but with zeroed outputs for all eventually-cancelled instructions is equivalent to our real CPU design #22

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opened 2025-08-26 07:15:34 +00:00 by programmerjake · 0 comments

programmerjake commented

2025-08-26 07:15:34 +00:00

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Issue for tracking progress of a subtask of NLnet grant 2024-12-324:
Attempt Proof that our CPU but with zeroed outputs for all eventually-cancelled instructions is equivalent to our real CPU design. This may need significant modifications to the CPU. This task may be too big and need further subdividing once we've made some progress on the proof so we know where to subdivide it.

Issue for tracking progress of a subtask of [NLnet grant 2024-12-324](https://git.libre-chip.org/libre-chip/grant-tracking/src/branch/master/nlnet-2024-12-324/progress.md): Attempt Proof that our CPU but with zeroed outputs for all eventually-cancelled instructions is equivalent to our real CPU design. This may need significant modifications to the CPU. This task may be too big and need further subdividing once we've made some progress on the proof so we know where to subdivide it.

programmerjake added this to the NLnet 2024-12-324 Libre-Chip's First CPU Architecture And Formal Proof of No Spectre bugs project 2025-08-26 07:15:34 +00:00

programmerjake added a new dependency 2025-08-26 08:11:29 +00:00

#21 NLnet 2024-12-324 Write Rocq and HDL logic for tracking which instructions will eventually be cancelled and which will eventually be retired.

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#21 NLnet 2024-12-324 Write Rocq and HDL logic for tracking which instructions will eventually be cancelled and which will eventually be retired.

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Reference: libre-chip/grant-tracking#22

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