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220 commits

Author SHA1 Message Date
Jacob Lifshay e0f978fbb6
silence unused m variable warning in #[hdl_module] with an empty body. 2025-03-27 23:17:28 -07:00
Jacob Lifshay ec3a61513b
simulator read/write types must be passive 2025-03-27 23:03:44 -07:00
Jacob Lifshay fdc73b5f3b
add ripple counter test to test simulating alternating circuits and extern modules 2025-03-25 18:56:26 -07:00
Jacob Lifshay a115585d5a
simulator: allow external module generators to wait for value changes and/or clock edges 2025-03-25 18:26:48 -07:00
Jacob Lifshay ab9ff4f2db
simplify setting an extern module simulation 2025-03-21 17:08:29 -07:00
Jacob Lifshay d1bd176b28
implement simulation of extern modules 2025-03-21 01:47:14 -07:00
Jacob Lifshay 920d8d875f
add some missing #[track_caller] 2025-03-19 17:10:51 -07:00
Jacob Lifshay d453755bb2
add ExprPartialEq/ExprPartialOrd impls for PhantomConst 2025-03-10 19:40:03 -07:00
Jacob Lifshay 450e1004b6
fix using fayalite as a dependency 2025-03-09 23:14:14 -07:00
Jacob Lifshay c0c5b550bc
add PhantomConst 2025-03-09 21:03:47 -07:00
Jacob Lifshay 2fa0ea6192
make FillInDefaultedGenerics work with Sizes and not just Types 2025-03-09 20:59:21 -07:00
Jacob Lifshay bd75fdfefd
add efficient prefix-sums and reductions 2025-03-02 23:04:17 -08:00
Jacob Lifshay 50c86e18dc
add Expr<ArrayType<T, Len>>: IntoIterator and Expr<Array<T>>: FromIterator<T> 2025-03-02 18:02:34 -08:00
Jacob Lifshay 60734cc9d1
switch CI to use mirrors 2025-03-02 17:43:29 -08:00
Jacob Lifshay 3458c21f44
add #[hdl(cmp_eq)] to implement HdlPartialEq automatically 2025-02-16 20:48:16 -08:00
Jacob Lifshay 43797db36e
sort custom keywords 2025-02-16 20:46:54 -08:00
Jacob Lifshay cdd84953d0
support unknown trait bounds in type parameters 2025-02-13 18:35:30 -08:00
Jacob Lifshay 86a1bb46be
add #[hdl] let destructuring and, while at it, tuple patterns 2025-02-10 22:49:41 -08:00
Jacob Lifshay 209d5b5fe1
fix broken doc links 2025-02-10 22:49:16 -08:00
Jacob Lifshay d4ea826051
sim: fix "label address not set" bug when the last Assignment is conditional 2025-01-15 19:04:40 -08:00
Jacob Lifshay 404a2ee043
tests/sim: add test_array_rw 2025-01-12 21:38:59 -08:00
Jacob Lifshay e3a2ccd41c
properly handle duplicate names in vcd 2025-01-09 22:52:22 -08:00
Cesar Strauss 3771cea78e
Gather the FIFO debug ports in a bundle 2024-12-29 13:17:24 -03:00
Cesar Strauss dcf865caec
Add assertions and debug ports in order for the FIFO to pass induction 
As some proofs involving memories, it is necessary to add more ports to
the queue interface, to sync state. These changes are predicated on the
test environment, so normal use is not affected.

Since some speedup is achieved, use the saved time to test with a deeper
FIFO.
 2024-12-29 13:12:58 -03:00
Cesar Strauss 31d01046a8
Initial queue formal proof based on one-entry FIFO equivalence 
For now, only check that the basic properties work in bounded model check
mode, leave the induction proof for later.

Partially replace the previously existing proof.

Remove earlier assumptions and bounds that don't apply for this proof.

Use parameterized types instead of hard-coded types.
 2024-12-29 13:04:01 -03:00
Jacob Lifshay c16726cee6
fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s 2024-12-29 00:48:15 -08:00
Jacob Lifshay b63676d0ca
add test for cfgs 2024-12-28 23:39:50 -08:00
Jacob Lifshay 7005fa3330
implement handling #[cfg] and #[cfg_attr] in proc macro inputs 2024-12-28 23:39:08 -08:00
Jacob Lifshay 2ab8428062
upgrade syn version 2024-12-28 23:39:08 -08:00
Jacob Lifshay 9b06019bf5
make sim::Compiler not print things to stdout unless you ask for it 2024-12-18 21:15:09 -08:00
Jacob Lifshay 36bad52978
sim: fix sim.write to struct 2024-12-18 20:50:50 -08:00
Jacob Lifshay 21c73051ec
sim: add SimValue and reading/writing more than just a scalar 2024-12-18 01:39:35 -08:00
Jacob Lifshay 304d8da0e8
Merge remote-tracking branch 'origin/master' into adding-simulator 2024-12-13 15:06:45 -08:00
Jacob Lifshay 2af38de900
add more memory tests 2024-12-13 15:04:48 -08:00
Jacob Lifshay c756aeec70
tests/sim: add test for memory rw port 2024-12-12 20:50:41 -08:00
Jacob Lifshay 903ca1bf30
sim: simple memory test works! 2024-12-12 19:47:57 -08:00
Jacob Lifshay 8d030ac65d
sim/interpreter: add addresses to instruction listing 2024-12-12 16:25:38 -08:00
Jacob Lifshay 562c479b62
sim/interpreter: fix StatePartLayout name in debug output 2024-12-12 15:06:17 -08:00
Jacob Lifshay 393f78a14d
sim: add WIP memory test 2024-12-11 23:28:15 -08:00
Jacob Lifshay 8616ee4737
tests/sim: test_enums works! 2024-12-11 00:01:04 -08:00
Jacob Lifshay 5087f16099
sim: fix assignments graph by properly including conditions as assignment inputs 2024-12-11 00:00:21 -08:00
Jacob Lifshay 6b31e6d515
sim: add .dot output for Assignments graph for debugging 2024-12-10 23:40:33 -08:00
Jacob Lifshay 564ccb30bc
sim/vcd: fix variable identifiers to follow verilog rules 2024-12-10 23:39:17 -08:00
Jacob Lifshay ca759168ff
tests/sim: add WIP test for enums 2024-12-10 23:37:26 -08:00
Jacob Lifshay e4cf66adf8
sim: implement memories, still needs testing 2024-12-09 23:03:01 -08:00
Jacob Lifshay cd0dd7b7ee
change memory write latency to NonZeroUsize to match read latency being usize 2024-12-09 23:01:40 -08:00
Cesar Strauss 2e7d685dc7 add module exercising formal verification of memories 2024-12-08 17:13:26 -03:00
Jacob Lifshay 9654167ca3
sim: WIP working on memory 2024-12-06 15:53:34 -08:00
Jacob Lifshay 3ed7827485
sim: WIP adding memory support 2024-12-05 21:35:23 -08:00
Jacob Lifshay e504cfebfe
add BoolOrIntType::copy_bits_from_bigint_wrapping and take BigInt arguments by reference 2024-12-05 20:32:15 -08:00