62058dc141
fix cargo doc warnings -- convert urls to auto links
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2025-04-01 22:22:54 -07:00
c4b6a0fee6
add support for #[hdl(sim)] enum_ty.Variant(value) and #[hdl(sim)] EnumTy::Variant(value) and non-sim variants too
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2025-04-01 22:16:47 -07:00
9092e45447
fix #[hdl(sim)] match on enums
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2025-03-30 01:25:07 -07:00
a40eaaa2da
expand SimValue support
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2025-03-30 00:55:38 -07:00
5028401a5a
change SimValue to contain and deref to a value and not just contain bits
2025-03-27 23:44:36 -07:00
e0f978fbb6
silence unused m variable warning in #[hdl_module] with an empty body.
2025-03-27 23:17:28 -07:00
ec3a61513b
simulator read/write types must be passive
2025-03-27 23:03:44 -07:00
fdc73b5f3b
add ripple counter test to test simulating alternating circuits and extern modules
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2025-03-25 18:56:26 -07:00
a115585d5a
simulator: allow external module generators to wait for value changes and/or clock edges
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2025-03-25 18:26:48 -07:00
ab9ff4f2db
simplify setting an extern module simulation
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2025-03-21 17:08:29 -07:00
d1bd176b28
implement simulation of extern modules
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2025-03-21 01:47:14 -07:00
920d8d875f
add some missing #[track_caller]
2025-03-19 17:10:51 -07:00
d453755bb2
add ExprPartialEq/ExprPartialOrd impls for PhantomConst
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2025-03-10 19:40:03 -07:00
450e1004b6
fix using fayalite as a dependency
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2025-03-09 23:14:14 -07:00
c0c5b550bc
add PhantomConst
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2025-03-09 21:03:47 -07:00
2fa0ea6192
make FillInDefaultedGenerics work with Sizes and not just Types
2025-03-09 20:59:21 -07:00
bd75fdfefd
add efficient prefix-sums and reductions
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2025-03-02 23:04:17 -08:00
50c86e18dc
add Expr<ArrayType<T, Len>>: IntoIterator and Expr<Array<T>>: FromIterator<T>
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2025-03-02 18:02:34 -08:00
3458c21f44
add #[hdl(cmp_eq)] to implement HdlPartialEq automatically
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2025-02-16 20:48:16 -08:00
43797db36e
sort custom keywords
2025-02-16 20:46:54 -08:00
cdd84953d0
support unknown trait bounds in type parameters
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2025-02-13 18:35:30 -08:00
86a1bb46be
add #[hdl] let destructuring and, while at it, tuple patterns
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2025-02-10 22:49:41 -08:00
209d5b5fe1
fix broken doc links
2025-02-10 22:49:16 -08:00
d4ea826051
sim: fix "label address not set" bug when the last Assignment is conditional
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2025-01-15 19:04:40 -08:00
404a2ee043
tests/sim: add test_array_rw
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2025-01-12 21:38:59 -08:00
e3a2ccd41c
properly handle duplicate names in vcd
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2025-01-09 22:52:22 -08:00
3771cea78e
Gather the FIFO debug ports in a bundle
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2024-12-29 13:17:24 -03:00
dcf865caec
Add assertions and debug ports in order for the FIFO to pass induction
...
As some proofs involving memories, it is necessary to add more ports to
the queue interface, to sync state. These changes are predicated on the
test environment, so normal use is not affected.
Since some speedup is achieved, use the saved time to test with a deeper
FIFO.
2024-12-29 13:12:58 -03:00
31d01046a8
Initial queue formal proof based on one-entry FIFO equivalence
...
For now, only check that the basic properties work in bounded model check
mode, leave the induction proof for later.
Partially replace the previously existing proof.
Remove earlier assumptions and bounds that don't apply for this proof.
Use parameterized types instead of hard-coded types.
2024-12-29 13:04:01 -03:00
c16726cee6
fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s
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2024-12-29 00:48:15 -08:00
b63676d0ca
add test for cfgs
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2024-12-28 23:39:50 -08:00
7005fa3330
implement handling #[cfg] and #[cfg_attr] in proc macro inputs
2024-12-28 23:39:08 -08:00
9b06019bf5
make sim::Compiler not print things to stdout unless you ask for it
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2024-12-18 21:15:09 -08:00
36bad52978
sim: fix sim.write to struct
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2024-12-18 20:50:50 -08:00
21c73051ec
sim: add SimValue and reading/writing more than just a scalar
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2024-12-18 01:39:35 -08:00
304d8da0e8
Merge remote-tracking branch 'origin/master' into adding-simulator
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2024-12-13 15:06:45 -08:00
2af38de900
add more memory tests
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2024-12-13 15:04:48 -08:00
c756aeec70
tests/sim: add test for memory rw port
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2024-12-12 20:50:41 -08:00
903ca1bf30
sim: simple memory test works!
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2024-12-12 19:47:57 -08:00
8d030ac65d
sim/interpreter: add addresses to instruction listing
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2024-12-12 16:25:38 -08:00
562c479b62
sim/interpreter: fix StatePartLayout name in debug output
2024-12-12 15:06:17 -08:00
393f78a14d
sim: add WIP memory test
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2024-12-11 23:28:15 -08:00
8616ee4737
tests/sim: test_enums works!
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2024-12-11 00:01:04 -08:00
5087f16099
sim: fix assignments graph by properly including conditions as assignment inputs
2024-12-11 00:00:21 -08:00
6b31e6d515
sim: add .dot output for Assignments graph for debugging
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2024-12-10 23:40:33 -08:00
564ccb30bc
sim/vcd: fix variable identifiers to follow verilog rules
2024-12-10 23:39:17 -08:00
ca759168ff
tests/sim: add WIP test for enums
2024-12-10 23:37:26 -08:00
e4cf66adf8
sim: implement memories, still needs testing
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2024-12-09 23:03:01 -08:00
cd0dd7b7ee
change memory write latency to NonZeroUsize to match read latency being usize
2024-12-09 23:01:40 -08:00
Cesar Strauss
2e7d685dc7
add module exercising formal verification of memories
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2024-12-08 17:13:26 -03:00
