Cesar Strauss dcf865caec Add assertions and debug ports in order for the FIFO to pass induction ... As some proofs involving memories, it is necessary to add more ports to the queue interface, to sync state. These changes are predicated on the test environment, so normal use is not affected. Since some speedup is achieved, use the saved time to test with a deeper FIFO.		2024-12-29 13:12:58 -03:00
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fayalite	Add assertions and debug ports in order for the FIFO to pass induction	2024-12-29 13:12:58 -03:00
fayalite-proc-macros	clean up deps and move missed deps to workspace	2024-09-25 01:22:35 -07:00
fayalite-proc-macros-impl	fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s	2024-12-29 00:48:15 -08:00
fayalite-visit-gen	clean up deps and move missed deps to workspace	2024-09-25 01:22:35 -07:00