mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity
15826 commits 122 branches 59 tags 73 MiB
Commit graph

140 commits

Author SHA1 Message Date
Claire Wolf
ed4fa19ba2 Update Copyright 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-03-16 16:28:25 +01:00
Waldir Pimenta
418c069561 License: bump year and add title 2020-03-14 16:46:07 +00:00
Eddie Hung
0f4c1906bb Small fixes 2020-02-27 10:29:53 -08:00
Eddie Hung
12d70ca8fb xilinx: improve specify functionality 2020-02-27 10:17:29 -08:00
Eddie Hung
577545488a xilinx: use specify blocks in place of abc9_{arrival,required} 2020-02-27 10:17:29 -08:00
Claire Wolf
cd044a2bb6
Merge pull request #1642 from jjj11x/jjj11x/sv-enum 
Enum support
 2020-02-20 18:17:25 +01:00
Jeff Wang
1c16311d10 update documentation for enums and typedefs 2020-02-17 04:42:55 -05:00
Miodrag Milanović
a7df492243
Add comment for macOS dependency install 2020-02-15 09:44:32 +01:00
Eddie Hung
0671ae7d79
Merge pull request #1661 from YosysHQ/eddie/abc9_required 
abc9: add support for required times
 2020-02-05 18:59:40 +01:00
David Shah
0488492ad2 Update CHANGELOG and README 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:13:13 +00:00
Eddie Hung
e0bdf5d7a9 Fix typo 2020-01-27 12:30:39 -08:00
Eddie Hung
168c9d5871 Update README.md for (* abc9_required *) 2020-01-15 14:42:00 -08:00
Eddie Hung
ffd38cb5ea Reword (* abc9_flop *) description 2020-01-06 09:03:18 -08:00
Eddie Hung
c40b1aae42 Restore abc9 -keepff 2020-01-01 08:34:43 -08:00
Eddie Hung
ece423415c Add CHANGELOG entry, add abc9_{flop,keep} attr to README.md 2019-12-30 14:24:58 -08:00
Eddie Hung
ff2645ce0b Put specify/endspecify inside `` 2019-12-20 13:38:32 -08:00
Eddie Hung
2666482282 Update README.md :: abc_ -> abc9_ 2019-12-11 16:38:43 -08:00
Marcin Kościelnicki
6cdea425b8 clkbufmap: Add support for inverters in clock path. 2019-11-25 20:40:39 +01:00
David Shah
b60f32c6ec Update CHANGELOG and README 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-22 12:46:19 +00:00
David Shah
1746b6373b Update CHANGELOG and README 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:45 +01:00
Marcin Kościelnicki
c9f9518de4 Added extractinv pass 2019-09-19 04:02:48 +02:00
Eddie Hung
903cd58acf
Merge pull request #1312 from YosysHQ/xaig_arrival 
Allow arrival times of sequential outputs to be specified to abc9
 2019-09-05 12:00:23 -07:00
Clifford Wolf
71d355560e Update README.md 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-05 17:20:29 +02:00
Clifford Wolf
30f1ac7ce9 Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes #1220 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-05 13:51:53 +02:00
Eddie Hung
c7f1ccbcb0 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-30 12:28:35 -07:00
Eddie Hung
999fb33fd0
Merge pull request #1340 from YosysHQ/eddie/abc_no_clean 
abc9 to not call "clean" at end of run (often called outside)
 2019-08-30 12:27:09 -07:00
Eddie Hung
d87a6f6303 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-30 10:32:58 -07:00
Eddie Hung
9c4e1c6a8f
Format -pwires 2019-08-30 10:27:07 -07:00
Eddie Hung
c52db44f9a Group abc_* attribute doc with other attributes 2019-08-29 12:13:52 -07:00
Eddie Hung
8d820a9884 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-28 15:19:10 -07:00
Eddie Hung
d672b1ddec Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-23 11:26:55 -07:00
Eddie Hung
4c0404ae02 Mention clkbuf_inhibit can be overridden 2019-08-23 10:24:59 -07:00
Eddie Hung
6872805a3e Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap 2019-08-23 10:00:50 -07:00
Miodrag Milanovic
c618ae43b9 Make macOS depenency clear 2019-08-23 10:37:50 +02:00
Clifford Wolf
e9f3eb9760 Bump year in copyright notice 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:43:16 +02:00
Eddie Hung
4cd1d21bfe Add (* abc_arrival=<int> *) doc 2019-08-20 18:27:16 -07:00
Eddie Hung
0ca397f087 Deprecate abc_scc_break attribute 2019-08-20 15:10:01 -07:00
Eddie Hung
29e4c8bd06 Clarify with 'only' 2019-08-19 10:00:53 -07:00
Eddie Hung
c36fca86f7 Update doc 2019-08-19 09:59:57 -07:00
Eddie Hung
d26c512d7e Add doc for abc_* attributes 2019-08-16 16:07:29 -07:00
Marcin Kościelnicki
2d5d82e2b6 README updates 2019-08-13 21:47:27 +02:00
Clifford Wolf
5be5bd0fb6 Update README to use "read" instead of "read_verilog" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-29 10:40:30 +02:00
David Shah
933db0410e Add support for reading gzip'd input files 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-26 10:23:58 +01:00
Roman-Parise
f7ab7a418c Updated FreeBSD dependencies in README.md 2019-07-14 09:25:07 -07:00
Clifford Wolf
ec4565009a Add "read_verilog -pwires" feature, closes #1106 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 14:38:50 +02:00
Clifford Wolf
8d0cd529c9 Add defaultvalue attribute 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 11:37:11 +02:00
Tux3
c66d644b66
README.md: Missing formatting for <tag> 2019-06-04 10:45:41 +02:00
Clifford Wolf
ba2185ead8 Refactor hierarchy wand/wor handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-28 16:43:25 +02:00
Stefan Biereigel
7f11a73210 update README.md with wand/wor information 2019-05-27 18:07:12 +02:00
Clifford Wolf
05a5027db8 Add $stop to documentation 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-09 15:31:40 +02:00