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xilinx: use specify blocks in place of abc9_{arrival,required}

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Eddie Hung 2020-02-11 14:22:43 -08:00
parent 0e7c55e2a7
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@ -364,25 +364,14 @@ Verilog Attributes and non-standard features
it as the external-facing pin of an I/O pad, and prevents ``iopadmap``
from inserting another pad cell on it.
- The module attribute ``abc9_box_id`` specifies a positive integer linking a
blackbox or whitebox definition to a corresponding entry in a `abc9`
box-file.
- The module attribute ``abc9_box`` is a boolean specifying a blackbox or
whitebox definition for use by `abc9`.
- The port attribute ``abc9_carry`` marks the carry-in (if an input port) and
carry-out (if output port) ports of a box. This information is necessary for
`abc9` to preserve the integrity of carry-chains. Specifying this attribute
onto a bus port will affect only its most significant bit.
- The output port attribute ``abc9_arrival`` specifies an integer, or a string
of space-separated integers to be used as the arrival time of this blackbox
port. It can be used, for example, to specify the clk-to-Q delay of a flip-
flop output for consideration during `abc9` techmapping.
- The input port attribute ``abc9_required`` specifies an integer, or a string
of space-separated integers to be used as the required time of this blackbox
port. It can be used, for example, to specify the setup-time of a flip-flop
input for consideration during `abc9` techmapping.
- The module attribute ``abc9_flop`` is a boolean marking the module as a
flip-flop. This allows `abc9` to analyse its contents in order to perform
sequential synthesis.