Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes #1220

Signed-off-by: Clifford Wolf <clifford@clifford.at>

README.md

@@ -332,6 +332,9 @@ Verilog Attributes and non-standard features
   that represent module parameters or localparams (when the HDL front-end
   is run in ``-pwires`` mode).
 
+- Wires marked with the ``hierconn`` attribute are connected to wires with the
+  same name when they are imported from sub-modules by ``flatten``.
+
 - The ``clkbuf_driver`` attribute can be set on an output port of a blackbox
   module to mark it as a clock buffer output, and thus prevent ``clkbufmap``
   from inserting another clock buffer on a net driven by such output.