mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-28 11:25:53 +00:00
Fix typo
This commit is contained in:
parent
f2576c096c
commit
e0bdf5d7a9
1 changed files with 1 additions and 1 deletions
|
@ -378,7 +378,7 @@ Verilog Attributes and non-standard features
|
|||
port. It can be used, for example, to specify the clk-to-Q delay of a flip-
|
||||
flop output for consideration during `abc9` techmapping.
|
||||
|
||||
- The input port attribute ``abc9_requiredl`` specifies an integer, or a string
|
||||
- The input port attribute ``abc9_required`` specifies an integer, or a string
|
||||
of space-separated integers to be used as the required time of this blackbox
|
||||
port. It can be used, for example, to specify the setup-time of a flip-flop
|
||||
input for consideration during `abc9` techmapping.
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue