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clkbufmap: Add support for inverters in clock path.

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Marcin Kościelnicki 2019-11-24 16:05:45 +01:00 • committed by Marcin Kościelnicki
parent 7562e7304e
commit 6cdea425b8
4 changed files with 69 additions and 6 deletions
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@ -343,6 +343,13 @@ Verilog Attributes and non-standard features
- The ``clkbuf_sink`` attribute can be set on an input port of a module to
request clock buffer insertion by the ``clkbufmap`` pass.
- The ``clkbuf_inv`` attribute can be set on an output port of a module
with the value set to the name of an input port of that module. When
the ``clkbufmap`` would otherwise insert a clock buffer on this output,
it will instead try inserting the clock buffer on the input port (this
is used to implement clock inverter cells that clock buffer insertion
will "see through").
- The ``clkbuf_inhibit`` is the default attribute to set on a wire to prevent
automatic clock buffer insertion by ``clkbufmap``. This behaviour can be
overridden by providing a custom selection to ``clkbufmap``.