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Add (* abc_arrival=<int> *) doc

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Eddie Hung 2019-08-20 18:27:16 -07:00
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@ -414,6 +414,11 @@ Verilog Attributes and non-standard features
`abc9` to preserve the integrity of carry-chains. Specifying this attribute
onto a bus port will affect only its most significant bit.
- The port attribute ``abc_arrival`` specifies an integer (for output ports
only) to be used as the arrival time of this sequential port. It can be used,
for example, to specify the clk-to-Q delay of a flip-flop for consideration
during techmapping.
Non-standard or SystemVerilog features for formal verification
==============================================================