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Add defaultvalue attribute
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -350,6 +350,10 @@ Verilog Attributes and non-standard features
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through the synthesis. When entities are combined, a new |-separated
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string is created that contains all the string from the original entities.
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- The ``defaultvalue`` attribute is used to store default values for
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module inputs. The attribute is attached to the input wire by the HDL
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front-end when the input is declared with a default value.
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- In addition to the ``(* ... *)`` attribute syntax, Yosys supports
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the non-standard ``{* ... *}`` attribute syntax to set default attributes
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for everything that comes after the ``{* ... *}`` statement. (Reset
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