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Add "read_verilog -pwires" feature, closes #1106

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Clifford Wolf 2019-06-19 14:38:50 +02:00
parent 5a1f1caa44
commit ec4565009a
6 changed files with 48 additions and 9 deletions
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@ -354,6 +354,10 @@ Verilog Attributes and non-standard features
module inputs. The attribute is attached to the input wire by the HDL
front-end when the input is declared with a default value.
- The ``parameter`` and ``localparam`` attributes are used to mark wires
that represent module parameters or localparams (when the HDL front-end
is run in -pwires mode).
- In addition to the ``(* ... *)`` attribute syntax, Yosys supports
the non-standard ``{* ... *}`` attribute syntax to set default attributes
for everything that comes after the ``{* ... *}`` statement. (Reset