1966 commits

Author	SHA1	Message	Date
Roland Coeurjoly	5ea2c6e6e5	Assume x values for missing signal data in FST ... Co-authored-by: Miodrag Milanovic <mmicko@gmail.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>	2024-10-02 12:08:48 +02:00
Emil J. Tywoniak	997cb30f1f	cxxrtl: test stream operator	2024-10-01 13:25:07 +02:00
Roland Coeurjoly	76c615b2ae	Fix: handle VCD variable references with and without whitespace ... Co-authored-by: Miodrag Milanović <mmicko@gmail.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>	2024-10-01 11:51:20 +02:00
rherveille	ce7db661a8	Added cast to type support (#4284)	2024-09-29 17:03:01 -04:00
George Rennie	0572f8806f	opt_reduce: add test for constant $reduce_and/or not being zero width	2024-09-25 16:28:41 +01:00
George Rennie	e105cae4a9	opt_demorgan: add test for zero width cell	2024-09-25 16:10:16 +01:00
Martin Povišer	ea765686b6	aiger2: Adjust hierarchy/port handling	2024-09-18 16:55:02 +02:00
Martin Povišer	6c1fa45995	aiger2: Ingest $pmux	2024-09-18 16:42:56 +02:00
Martin Povišer	d5756eb9be	tests: Add trivial liberty -unit_delay test	2024-09-18 16:17:03 +02:00
Martin Povišer	31476e89b6	tests: Avoid temporary script file	2024-09-18 16:17:03 +02:00
Martin Povišer	8e29675a23	aiger2: Support $bwmux, comparison operators	2024-09-17 13:55:58 +02:00
Martin Povišer	fb26945a20	Start an 'aiger2' backend	2024-09-17 13:55:58 +02:00
Martin Povišer	4cfdb7ab50	Adjust operation naming in aigmap test	2024-09-17 13:55:58 +02:00
Emil J	52382c6544	Merge pull request #4583 from YosysHQ/emil/clock_gate ... clockgate: centralize clock enables out of FFs	2024-09-16 15:41:01 +02:00
N. Engelhardt	c8b42b7d48	Merge pull request #4538 from RCoeurjoly/verific_bounds	2024-09-12 13:04:04 +02:00
Emil J. Tywoniak	1e999a3cb7	clockgate: EN can be a bit on a multi-bit wire	2024-09-11 19:18:25 +02:00
Roland Coeurjoly	bdc43c6592	Add left and right bound properties to wire. Add test. Fix printing ... for signed attributes Co-authored-by: N. Engelhardt <nak@yosyshq.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>	2024-09-10 12:52:42 +02:00
Emil J. Tywoniak	7e473299bd	clockgate: bail on constant signals	2024-09-09 21:20:19 +02:00
Emil J. Tywoniak	dc039d8be4	clockgate: test fine-grained cells	2024-09-09 21:03:22 +02:00
Emil J. Tywoniak	e64fceef70	clockgate: prototype clock gating	2024-09-09 15:00:54 +02:00
Miodrag Milanović	b20df72e1e	Merge pull request #4536 from YosysHQ/functional ... Functional Backend	2024-09-06 10:05:04 +02:00
Emily Schmidt	5a476a8d29	functional tests: run from make tests but not smtlib/rkt tests	2024-09-04 10:30:08 +01:00
Krystine Sherwin	7fe9157df2	smtr: Add rkt to functional tests	2024-09-03 11:32:02 +01:00
Miodrag Milanović	598d010349	Merge pull request #4504 from YosysHQ/nanoxplore ... NanoXplore synthesis	2024-09-03 10:19:44 +02:00
Emily Schmidt	2b8db94aa0	functional backend: add test to verify test_generic	2024-08-29 13:14:18 +01:00
George Rennie	8206951f77	proc_dff: add tests	2024-08-28 16:24:47 +01:00
Emily Schmidt	761eff594f	functional backend: missing includes for stl containers	2024-08-22 11:13:58 +01:00
Roland Coeurjoly	91e3773b51	Ensure signed constants are correctly parsed, represented, and exported in RTLIL. Add a test to check parsing and exporting	2024-08-21 14:28:42 +01:00
Emily Schmidt	831da51255	add picorv test to functional backend	2024-08-21 11:04:11 +01:00
Emily Schmidt	99effb6789	add support for initializing registers and memories to the functional backend	2024-08-21 11:03:29 +01:00
Emily Schmidt	145af6f10d	fix memory handling in functional backend, add more error messages and comments for memory edgecases	2024-08-21 11:03:29 +01:00
Emily Schmidt	3cd5f4ed83	add support for RTLIL cells with multiple outputs to the functional backend, implement $fa,$lcu,$alu	2024-08-21 11:03:29 +01:00
Emily Schmidt	c0c90c2c31	functional backend: require shift width == clog2(operand width)	2024-08-21 11:03:29 +01:00
Emily Schmidt	6922633b0b	fix a few bugs in the functional backend and refactor the testing	2024-08-21 11:03:29 +01:00
Emily Schmidt	674e6d201d	rewrite functional backend test code in python	2024-08-21 11:03:29 +01:00
Roland Coeurjoly	80582ed3af	Check the existance of a different set of outputs. No need for (push 1) nor (pop 1)	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	7cff8fa3a3	Fix corner case of pos cell with input and output being same width	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	5780357cd9	Emit valid SMT for stateful designs, fix some cells	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	50f487e08c	Added $ff test	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	762f8dd822	Add readme explaining how to create test files	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	73ed514623	Check that there are not other solutions other than the first given	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	cb5f08364c	´SMT success only if simulation is equivalent	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	e235fc704d	Create std::mt19937 only once	2024-08-21 11:02:31 +01:00
Emily Schmidt	21bb1cf1bc	rewrite functional c++ simulation library	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	39bf4f04f7	Create VCD file from SMT file	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	b98210d8ac	Valid SMT is emitted, improved test script	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	71aaa1c80d	Consolidate tests scripts into one	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	547c5466ec	Ignore smt2 files, generated by the execution of the tests	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	54225b5c42	Add test for SMT backend. Tests if SMT is valid and compares simulation with yosys sim	2024-08-21 11:02:31 +01:00
Roland Coeurjoly	720429b1fd	Add test_cell tests for C++ functional backend	2024-08-21 11:01:09 +01:00