mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-23 00:55:32 +00:00
functional backend: require shift width == clog2(operand width)
This commit is contained in:
parent
7f8f21b980
commit
c0c90c2c31
3 changed files with 34 additions and 29 deletions
|
@ -206,7 +206,10 @@ shift_widths = [
|
|||
(32, 32, 64, True, True),
|
||||
(32, 32, 64, False, True),
|
||||
# at least one test where the result is going to be truncated
|
||||
(32, 6, 16, False, False)
|
||||
(32, 6, 16, False, False),
|
||||
# since 1-bit shifts are special cased
|
||||
(1, 4, 1, False, False),
|
||||
(1, 4, 1, True, False),
|
||||
]
|
||||
|
||||
rtlil_cells = [
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue