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fix memory handling in functional backend, add more error messages and comments for memory edgecases

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This commit is contained in:
Emily Schmidt 2024-07-18 14:10:15 +01:00
parent 4722f13a5d
commit 145af6f10d
3 changed files with 86 additions and 17 deletions
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45
tests/functional/rtlil_cells.py
View file

@ -176,14 +176,52 @@ module gold(
input wire clk,
input wire [{1}:0] WA,
input wire [{0}:0] WD,
input wire [{1}:0] RA,
output reg [{0}:0] RD
);
reg [{0}:0] mem[0:{1}];
reg [{0}:0] mem[0:{2}];
always @(*)
RD = mem[RA];
always @(posedge clk)
mem[WA] <= WD;
endmodule""".format(parameters['DATA_WIDTH'] - 1, parameters['ADDR_WIDTH'] - 1))
endmodule""".format(parameters['DATA_WIDTH'] - 1, parameters['ADDR_WIDTH'] - 1, 2**parameters['ADDR_WIDTH'] - 1))
yosys_synth(verilog_file, path)
class MemDualCell(BaseCell):
def __init__(self, name, values):
super().__init__(name, ['DATA_WIDTH', 'ADDR_WIDTH'],
{'WA1': 'ADDR_WIDTH', 'WA2': 'ADDR_WIDTH',
'RA1': 'ADDR_WIDTH', 'RA2': 'ADDR_WIDTH',
'WD1': 'DATA_WIDTH', 'WD2': 'DATA_WIDTH'},
{'RD1': 'DATA_WIDTH', 'RD2': 'DATA_WIDTH'}, values)
self.sim_preprocessing = "memory_map" # issue #4496 in yosys -sim prevents this example from working without memory_map
def write_rtlil_file(self, path, parameters):
from test_functional import yosys_synth
verilog_file = path.parent / 'verilog.v'
with open(verilog_file, 'w') as f:
f.write("""
module gold(
input wire clk,
input wire [{1}:0] WA1,
input wire [{0}:0] WD1,
input wire [{1}:0] WA2,
input wire [{0}:0] WD2,
input wire [{1}:0] RA1,
input wire [{1}:0] RA2,
output reg [{0}:0] RD1,
output reg [{0}:0] RD2
);
(*keep*)
reg [{0}:0] mem[0:{2}];
always @(*)
RD1 = mem[RA1];
always @(*)
RD2 = mem[RA2];
always @(posedge clk) begin
mem[WA1] <= WD1;
mem[WA2] <= WD2;
end
endmodule""".format(parameters['DATA_WIDTH'] - 1, parameters['ADDR_WIDTH'] - 1, 2**parameters['ADDR_WIDTH'] - 1))
yosys_synth(verilog_file, path)
binary_widths = [
@ -284,7 +322,8 @@ rtlil_cells = [
BWCell("bweqx", [10, 16, 40]),
BWCell("bwmux", [10, 16, 40]),
FFCell("ff", [10, 20, 40]),
MemCell("mem", [(32, 4)])
MemCell("mem", [(16, 4)]),
MemDualCell("mem-dual", [(16, 4)]),
# ("assert", ["A", "EN"]),
# ("assume", ["A", "EN"]),
# ("live", ["A", "EN"]),

6
tests/functional/test_functional.py
View file

@ -24,7 +24,7 @@ def compile_cpp(in_path, out_path, args):
run(['g++', '-g', '-std=c++17'] + args + [str(in_path), '-o', str(out_path)])
def yosys_synth(verilog_file, rtlil_file):
yosys(f"read_verilog {quote(verilog_file)} ; prep ; clk2fflogic ; write_rtlil {quote(rtlil_file)}")
yosys(f"read_verilog {quote(verilog_file)} ; prep ; write_rtlil {quote(rtlil_file)}")
# simulate an rtlil file with yosys, comparing with a given vcd file, and writing out the yosys simulation results into a second vcd file
def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""):
@ -49,7 +49,7 @@ def test_cxx(cell, parameters, tmp_path, num_steps, rnd):
vcd_yosys_sim_file = tmp_path / 'yosys.vcd'
cell.write_rtlil_file(rtlil_file, parameters)
yosys(f"read_rtlil {quote(rtlil_file)} ; write_functional_cxx {quote(cc_file)}")
yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_cxx {quote(cc_file)}")
compile_cpp(vcdharness_cc_file, vcdharness_exe_file, ['-I', tmp_path, '-I', str(base_path / 'backends/functional/cxx_runtime')])
seed = str(rnd(cell.name + "-cxx").getrandbits(32))
run([str(vcdharness_exe_file.resolve()), str(vcd_functional_file), str(num_steps), str(seed)])
@ -64,7 +64,7 @@ def test_smt(cell, parameters, tmp_path, num_steps, rnd):
vcd_yosys_sim_file = tmp_path / 'yosys.vcd'
cell.write_rtlil_file(rtlil_file, parameters)
yosys(f"read_rtlil {quote(rtlil_file)} ; write_functional_smt2 {quote(smt_file)}")
yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_smt2 {quote(smt_file)}")
run(['z3', smt_file]) # check if output is valid smtlib before continuing
smt_vcd.simulate_smt(smt_file, vcd_functional_file, num_steps, rnd(cell.name + "-smt"))
yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))