Add test_cell tests for C++ functional backend

tests/functional/.gitignore

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+my_module_cxxrtl.cc
+my_module_functional_cxx.cc
+vcd_harness
+*.vcd

tests/functional/single_cells/rtlil/test_cell_add_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 5 input 1 \A
+  wire width 4 input 2 \B
+  wire width 6 output 3 \Y
+  cell $add \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 5
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_alu_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 8 input 1 \A
+  wire width 7 input 2 \B
+  wire input 3 \BI
+  wire input 4 \CI
+  wire width 6 output 5 \CO
+  wire width 6 output 6 \X
+  wire width 6 output 7 \Y
+  cell $alu \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 8
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \BI \BI
+    connect \CI \CI
+    connect \CO \CO
+    connect \X \X
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_and_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 2 input 1 \A
+  wire width 3 input 2 \B
+  wire width 2 output 3 \Y
+  cell $and \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_bmux_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 8 input 1 \A
+  wire input 2 \S
+  wire width 4 output 3 \Y
+  cell $bmux \UUT
+    parameter \S_WIDTH 1
+    parameter \WIDTH 4
+    connect \A \A
+    connect \S \S
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_demux_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 6 input 1 \A
+  wire width 5 input 2 \S
+  wire width 192 output 3 \Y
+  cell $demux \UUT
+    parameter \S_WIDTH 5
+    parameter \WIDTH 6
+    connect \A \A
+    connect \S \S
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_div_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 4 input 1 \A
+  wire width 6 input 2 \B
+  wire output 3 \Y
+  cell $div \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 6
+    parameter \Y_WIDTH 1
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 4 input 1 \A
+  wire width 4 input 2 \B
+  wire width 6 output 3 \Y
+  cell $divfloor \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_eq_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 5 input 1 \A
+  wire input 2 \B
+  wire width 4 output 3 \Y
+  cell $eq \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 5
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_fa_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire input 1 \A
+  wire input 2 \B
+  wire input 3 \C
+  wire output 4 \X
+  wire output 5 \Y
+  cell $fa \UUT
+    parameter \WIDTH 1
+    connect \A \A
+    connect \B \B
+    connect \C \C
+    connect \X \X
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_ge_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 3 input 1 \A
+  wire width 7 input 2 \B
+  wire width 6 output 3 \Y
+  cell $ge \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_gt_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 7 input 1 \A
+  wire width 3 input 2 \B
+  wire width 4 output 3 \Y
+  cell $gt \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_lcu_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire input 1 \CI
+  wire width 2 output 2 \CO
+  wire width 2 input 3 \G
+  wire width 2 input 4 \P
+  cell $lcu \UUT
+    parameter \WIDTH 2
+    connect \CI \CI
+    connect \CO \CO
+    connect \G \G
+    connect \P \P
+  end
+end

tests/functional/single_cells/rtlil/test_cell_le_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 5 input 1 \A
+  wire width 4 input 2 \B
+  wire width 6 output 3 \Y
+  cell $le \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 5
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_logic_and_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 2 input 1 \A
+  wire width 7 input 2 \B
+  wire output 3 \Y
+  cell $logic_and \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 1
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_logic_not_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 3 input 1 \A
+  wire width 8 output 2 \Y
+  cell $logic_not \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 8
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_logic_or_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 8 input 1 \A
+  wire width 7 input 2 \B
+  wire width 2 output 3 \Y
+  cell $logic_or \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 8
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_lt_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 8 input 1 \A
+  wire width 5 input 2 \B
+  wire width 6 output 3 \Y
+  cell $lt \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 8
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_lut_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 2 input 1 \A
+  wire output 2 \Y
+  cell $lut \UUT
+    parameter \LUT 4'1111
+    parameter \WIDTH 2
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_macc_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 3 input 1 \A
+  wire width 0 input 2 \B
+  wire width 2 output 3 \Y
+  cell $macc \UUT
+    parameter \A_WIDTH 3
+    parameter \B_WIDTH 0
+    parameter \CONFIG 10'0110000010
+    parameter \CONFIG_WIDTH 10
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B { }
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_mod_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 6 input 1 \A
+  wire width 8 input 2 \B
+  wire width 2 output 3 \Y
+  cell $mod \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 6
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 8
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_modfloor_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 5 input 1 \A
+  wire width 7 input 2 \B
+  wire width 4 output 3 \Y
+  cell $modfloor \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 5
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_mul_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 6 input 1 \A
+  wire width 2 input 2 \B
+  wire width 5 output 3 \Y
+  cell $mul \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 6
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 5
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_mux_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 4 input 1 \A
+  wire width 4 input 2 \B
+  wire input 3 \S
+  wire width 4 output 4 \Y
+  cell $mux \UUT
+    parameter \WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \S \S
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_ne_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 7 input 1 \A
+  wire width 5 input 2 \B
+  wire width 4 output 3 \Y
+  cell $ne \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_neg_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 2 input 1 \A
+  wire width 5 output 2 \Y
+  cell $neg \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \Y_WIDTH 5
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_not_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 7 input 1 \A
+  wire width 7 output 2 \Y
+  cell $not \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 7
+    parameter \Y_WIDTH 7
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_or_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 7 input 1 \A
+  wire input 2 \B
+  wire width 2 output 3 \Y
+  cell $or \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_pos_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire input 1 \A
+  wire width 3 output 2 \Y
+  cell $pos \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 3
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_reduce_and_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 4 input 1 \A
+  wire width 5 output 2 \Y
+  cell $reduce_and \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 5
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_reduce_bool_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire input 1 \A
+  wire width 2 output 2 \Y
+  cell $reduce_bool \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_reduce_or_00000.il

@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 2 input 1 \A
+  wire width 7 output 2 \Y
+  cell $reduce_or \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \Y_WIDTH 7
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_reduce_xnor_00000.il

@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 4 input 1 \A
+  wire width 4 output 2 \Y
+  cell $reduce_xnor \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_reduce_xor_00000.il

@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 4 input 1 \A
+  wire output 2 \Y
+  cell $reduce_xor \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_shift_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire input 1 \A
+  wire width 6 input 2 \B
+  wire width 4 output 3 \Y
+  cell $shift \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 6
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_shiftx_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire input 1 \A
+  wire width 5 input 2 \B
+  wire width 3 output 3 \Y
+  cell $shiftx \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 3
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_shl_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 8 input 1 \A
+  wire width 2 input 2 \B
+  wire width 3 output 3 \Y
+  cell $shl \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 8
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 3
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_shr_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 7 input 1 \A
+  wire width 6 input 2 \B
+  wire width 4 output 3 \Y
+  cell $shr \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 6
+    parameter \Y_WIDTH 4
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_sop_00000.il

@@ -0,0 +1,13 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 8 input 1 \A
+  wire output 2 \Y
+  cell $sop \UUT
+    parameter \DEPTH 8
+    parameter \TABLE 128'10010000100100000101101010001001101000101010010100010000010100000101010100000001001010010110101010101010101000100100011001000110
+    parameter \WIDTH 8
+    connect \A \A
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_sshl_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 5 input 1 \A
+  wire width 3 input 2 \B
+  wire width 6 output 3 \Y
+  cell $sshl \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 5
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_sshr_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 3 input 1 \A
+  wire width 2 input 2 \B
+  wire width 2 output 3 \Y
+  cell $sshr \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_sub_00000.il

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+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 6 input 1 \A
+  wire width 6 input 2 \B
+  wire width 6 output 3 \Y
+  cell $sub \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 6
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 6
+    parameter \Y_WIDTH 6
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_xnor_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 7 input 1 \A
+  wire width 8 input 2 \B
+  wire width 7 output 3 \Y
+  cell $xnor \UUT
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 1
+    parameter \B_WIDTH 8
+    parameter \Y_WIDTH 7
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/rtlil/test_cell_xor_00000.il

@@ -0,0 +1,17 @@
+# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
+autoidx 1
+module \gold
+  wire width 6 input 1 \A
+  wire width 2 input 2 \B
+  wire width 8 output 3 \Y
+  cell $xor \UUT
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 6
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 8
+    connect \A \A
+    connect \B \B
+    connect \Y \Y
+  end
+end

tests/functional/single_cells/run-test.sh

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+#!/bin/bash
+
+# Initialize an array to store the names of failing RTLIL files and their failure types
+declare -A failing_files
+# Initialize an array to store the names of successful RTLIL files
+declare -A successful_files
+
+# Function to run the test on a given RTLIL file
+run_test() {
+    # Define the common variable for the relative path
+    BASE_PATH="../../../"
+
+    local rtlil_file=$1
+
+    # Extract the base name without extension
+    local base_name=$(basename "$rtlil_file" .v)
+    
+    # Run yosys to process each RTLIL file
+    if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; write_functional_cxx my_module_functional_cxx.cc"; then
+        echo "Yosys processed $rtlil_file successfully."
+        
+        # Compile the generated C++ files with vcd_harness.cpp
+        if ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cc -I ${BASE_PATH}backends/functional/cxx_runtime/ -std=c++17 -o vcd_harness; then
+            echo "Compilation successful."
+            # Generate VCD files with base_name
+            if ./vcd_harness ${base_name}_functional_cxx.vcd; then
+		
+		# Run yosys to process each RTLIL file
+		if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -r ${base_name}_functional_cxx.vcd -scope gold -vcd ${base_name}_yosys_sim.vcd -timescale 1us -sim-gold"; then
+		    echo "Yosys sim $rtlil_file successfully."
+		    successful_files["$rtlil_file"]="Success"
+		else
+		    ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys_sim.vcd -r ${base_name}_functional_cxx.vcd -scope gold -timescale 1us"
+		    echo "Yosys simulation of $rtlil_file failed. There is a discrepancy with functional cxx"
+		    failing_files["$rtlil_file"]="Yosys sim failure"
+		fi
+		
+            else
+		echo "Failed to generate VCD files for $rtlil_file."
+		failing_files["$rtlil_file"]="VCD generation failure"
+            fi
+	else
+	    echo "Failed to compile harness for $rtlil_file."
+	    failing_files["$rtlil_file"]="Compilation failure"
+	fi
+	else
+            echo "Yosys failed to process $rtlil_file."
+            failing_files["$rtlil_file"]="Yosys failure"
+	fi
+}
+
+# Main function to run all tests
+run_all_tests() {
+    # Loop through all RTLIL files in the rtlil directory
+    for rtlil_file in rtlil/*.il; do
+        run_test "$rtlil_file"
+    done
+
+    # Check if the array of failing files is empty
+    if [ ${#failing_files[@]} -eq 0 ]; then
+        echo "All files passed."
+	echo "The following files passed:"
+        for file in "${!successful_files[@]}"; do
+            echo "$file"
+        done
+        return 0
+    else
+        echo "The following files failed:"
+        for file in "${!failing_files[@]}"; do
+            echo "$file: ${failing_files[$file]}"
+        done
+	echo "The following files passed:"
+        for file in "${!successful_files[@]}"; do
+            echo "$file"
+        done
+        return 1
+    fi
+}
+
+# If the script is being sourced, do not execute the tests
+if [[ "${BASH_SOURCE[0]}" == "${0}" ]]; then
+    run_all_tests
+fi

tests/functional/single_cells/vcd_harness.cc

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+#include <cstdio>
+#include <iostream>
+#include <fstream>
+#include <random>
+
+#include "my_module_functional_cxx.cc"
+
+struct DumpHeader {
+  std::ofstream &ofs;
+  DumpHeader(std::ofstream &ofs) : ofs(ofs) {}
+  template <size_t n>
+  void operator()(const char *name, Signal<n> value) {
+    ofs << "$var wire " << n << " " << name[0] << " " << name << " $end\n";
+  }
+};
+
+struct Dump {
+  std::ofstream &ofs;
+  Dump(std::ofstream &ofs) : ofs(ofs) {}
+  template <size_t n>
+  void operator()(const char *name, Signal<n> value) {
+    // Bit
+    if (n == 1) {
+      ofs << (value[0] ? '1' : '0');
+      ofs << name[0] << "\n";
+      return;
+    }
+    // vector (multi-bit) signals
+    ofs << "b";
+    for (size_t i = n; i-- > 0;)
+      ofs << (value[i] ? '1' : '0');
+    ofs << " " << name[0] << "\n";
+  }
+};
+
+// Function to set all values in a signal to false
+template<std::size_t n>
+void set_all_false(Signal<n>& signal) {
+  std::fill(signal.begin(), signal.end(), false);
+}
+
+template<std::size_t n>
+void set_all_random(Signal<n>& signal) {
+  std::random_device rd;  // Random device for seeding
+  std::mt19937 gen(rd()); // Mersenne Twister engine
+  std::bernoulli_distribution dist(0.5); // 50-50 distribution
+
+  for (auto& value : signal) {
+    value = dist(gen); // Set each value to a random boolean
+  }
+}
+
+int main(int argc, char **argv)
+{
+  if (argc != 2) {
+    std::cerr << "Usage: " << argv[0] << " <functional_vcd_filename>\n";
+    return 1;
+  }
+
+  const std::string functional_vcd_filename = argv[1];
+
+  constexpr int steps = 10;
+  constexpr int number_timescale = 1;
+  const std::string units_timescale = "us";
+  gold_Inputs inputs;
+  gold_Outputs outputs;
+  gold_State state;
+  gold_State next_state;
+
+  std::ofstream vcd_file(functional_vcd_filename);
+
+  vcd_file << "$timescale " << number_timescale << " " << units_timescale << " $end\n";
+  vcd_file << "$scope module gold $end\n";
+  {
+    DumpHeader d(vcd_file);
+    inputs.dump(d);
+    outputs.dump(d);
+    state.dump(d);
+  }
+  vcd_file << "$enddefinitions $end\n$dumpvars\n";
+  vcd_file << "#0\n";
+  // Set all signals to false
+  for (int i = 0; i < inputs.size(); ++i) {
+    auto input_variant = inputs.get_input(i);
+    std::visit([](auto& signal_ref) {
+      set_all_false(signal_ref.get());
+    }, input_variant);
+  }
+     
+  gold(inputs, outputs, state, next_state);
+  {
+    Dump d(vcd_file);
+    inputs.dump(d);
+    outputs.dump(d);
+    state.dump(d);
+  }
+    
+  for (int step = 0; step < steps; ++step) {
+    // Functional backend cxx
+    vcd_file << "#" << (step + 1) << "\n";
+    // Set all signals to random
+    for (int i = 0; i < inputs.size(); ++i) {
+      auto input_variant = inputs.get_input(i);
+      std::visit([](auto& signal_ref) {
+	set_all_random(signal_ref.get());
+      }, input_variant);
+    }
+
+    gold(inputs, outputs, state, next_state);
+    {
+      Dump d(vcd_file);
+      inputs.dump(d);
+      outputs.dump(d);
+      state.dump(d);
+    }
+	
+    state = next_state;
+  }
+
+  vcd_file.close();
+
+  return 0;
+}