Akash Levy
e3a6b920d4
Merge branch 'YosysHQ:main' into main
2025-06-02 18:47:14 +02:00
Emil J
c21cd300a0
Merge pull request #5109 from YosysHQ/emil/aiger-map-fix-outputs
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aiger: fix -map and -vmap
2025-06-02 15:07:19 +02:00
N. Engelhardt
1c742441db
Merge pull request #5150 from YosysHQ/krys/aiger_ordering
2025-06-02 13:06:36 +00:00
Krystine Sherwin
aac562d36a
aiger.cc: Explicit unsorted-pool-as-LIFO
2025-05-31 09:55:00 +12:00
Krystine Sherwin
0072a267cc
write_aiger: Add no-sort option
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Prevents sorting input/output bits so that they remain in the same order they were read in.
2025-05-29 16:20:16 +12:00
Akash Levy
3fc74be3e2
Merge branch 'YosysHQ:main' into main
2025-05-28 01:54:49 +02:00
gatecat
45a6940f40
cxxrtl: Add debug items for state with private names
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Signed-off-by: gatecat <gatecat@ds0.me>
2025-05-26 16:58:13 +02:00
Akash Levy
3a23e772dd
Merge branch 'YosysHQ:main' into main
2025-05-24 12:11:52 -07:00
Emil J
4b8d42d22c
Merge pull request #5095 from YosysHQ/emil/one-bit-width
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rtlil: enable single-bit vector wires
2025-05-23 15:55:45 +02:00
Emil J. Tywoniak
f73c6a9c9a
write_verilog: don't dump single_bit_vector attribute
2025-05-12 13:36:25 +02:00
Emil J. Tywoniak
5e72464a15
rtlil: enable single-bit vector wires
2025-05-12 13:23:29 +02:00
Akash Levy
aeed1ddb74
Update from upstream
2025-05-11 15:16:52 -07:00
Emil J. Tywoniak
2522bcd492
aiger: fix -map and -vmap
2025-05-09 14:21:10 +02:00
Emil J. Tywoniak
90a2c92370
driver: allow --no-version still write things like Generated by Yosys
2025-05-07 11:34:23 +02:00
Akash Levy
7191be492c
Merge branch 'YosysHQ:main' into main
2025-05-05 15:36:40 -07:00
Emil J. Tywoniak
d7affb8821
driver: add --no-version to suppress writing Yosys version in command outputs
2025-05-05 13:12:08 +02:00
sdjasj
da1ac9ae47
cxxrtl: fix missing sign extension before shift operation for signed values
2025-05-03 09:38:16 +00:00
Akash Levy
94bc6937d3
Merge branch 'YosysHQ:main' into main
2025-04-27 15:24:30 -07:00
Catherine
3d1f2161dc
cxxrtl: strip $paramod from module name in scope info.
2025-04-26 14:51:21 +01:00
Akash Levy
b8ee17e807
Merge branch 'YosysHQ:main' into main
2025-04-24 14:51:28 -07:00
sdjasj
b693947834
fix udivmod crashes when operand value exceeds logical width
2025-04-24 14:33:52 +01:00
Akash Levy
5f5ed1b29e
Merge upstream yosys
2025-04-21 17:36:24 -07:00
David Sawatzke
04098933c7
cxxrtl: Add internal cell "bwmux"
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Mirrors the implementation for the smt2 backend
Co-authored-by: Martin Povišer <povik@cutebit.org>
2025-04-16 13:58:08 +01:00
Akash Levy
e241c9d513
Merge branch 'YosysHQ:main' into main
2025-04-10 14:28:10 -07:00
Krystine Sherwin
cd3b914132
Reinstate #4768
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Revert the reversion so that we can fix the bugs that the PR missed.
2025-04-08 11:58:05 +12:00
Akash Levy
06c614a010
Merge branch 'YosysHQ:main' into main
2025-04-07 07:28:06 -07:00
Miodrag Milanović
d49364d96f
Revert "Refactor full_selection"
2025-04-07 12:11:55 +02:00
Akash Levy
0dab4308a3
Actual merge here
2025-04-06 18:53:43 -07:00
KrystalDelusion
98d4355b82
Merge pull request #4768 from YosysHQ/krys/refactor_selections
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Refactor full_selection
2025-04-05 14:15:27 +13:00
Akash Levy
f218b5ba58
Revert "Represent memory size with size_t"
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This reverts commit bb5f8415af
2025-04-04 03:20:07 -07:00
Akash Levy
bb5f8415af
Represent memory size with size_t
2025-04-04 02:04:34 -07:00
Akash Levy
95f489beec
Merge nice gzip refactor
2025-03-20 16:47:12 -07:00
Emil J. Tywoniak
4f3fdc8457
io: refactor string and file work into new unit
2025-03-19 13:43:42 +01:00
Akash Levy
1c0d4a43b3
Merge branch 'YosysHQ:main' into main
2025-03-14 18:07:55 -07:00
KrystalDelusion
9fa1f0e70c
Merge pull request #4567 from kivikakk/cxxrtl-escape-trailing
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cxxrtl: use octal encoding of non-printables.
2025-03-14 16:52:07 +13:00
Krystine Sherwin
46a311acb2
firrtl: Drop full_selection check
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Change `top` pointer default to `nullptr` to avoid issues with `Design->top_module()` only operating on the current selection.
Calls to other passes (`bmuxmap` etc) will only operate on the current selection, and may cause problems when those cells are unprocessed, but this is consistent with the other backends that only operate on the full designs and will hopefully be fixed in another PR soon :)
2025-03-14 14:08:56 +13:00
Krystine Sherwin
dac2bb7d4d
Use selection helpers
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Catch more uses of selection constructor without assigning a design.
2025-03-14 14:08:13 +13:00
Akash Levy
e4066b784d
Merge remote-tracking branch 'upstream/main'
2025-03-12 19:21:32 -07:00
KrystalDelusion
65748b8387
Merge pull request #4898 from Anhijkt/fix-xaiger-segfault
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write_xaiger: Detect and error on combinatorial loops
2025-03-13 10:49:48 +13:00
Akash Levy
e360511339
Merge branch 'YosysHQ:main' into main
2025-03-10 14:21:49 -07:00
Alain Dargelas
268459e00a
write_verilog -srcattronly option
2025-03-10 10:15:24 -07:00
Alain Dargelas
1b1882fe56
write_verilog -srcattronly option
2025-03-10 09:29:48 -07:00
Alain Dargelas
e35032f2f6
write_verilog -onlysrcattr option
2025-03-10 09:27:27 -07:00
N. Engelhardt
c74df780b7
Merge pull request #4884 from YosysHQ/docs-preview-functional_tutorial
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Docs: More on FunctionalIR
2025-03-10 15:05:55 +00:00
Anhijkt
a8052f653a
write_xaiger: Detect and error on combinatorial loops
2025-02-14 01:21:39 +02:00
Krystine Sherwin
fa2d45a922
smtr: Refactor write back into _eval and _initial
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Easier for comparisons, and the structure still works. (I don't remember why I moved away from it in the first place.)
2025-02-07 13:58:09 +13:00
Akash Levy
66186f11fd
Merge branch 'YosysHQ:main' into main
2025-01-30 14:00:19 -08:00
Robin Ole Heinemann
0ab13924a5
write_verilog: log_abort on unhandled $check flavor
2025-01-30 14:18:02 +00:00
Robin Ole Heinemann
2f11dc87c9
write_verilog: emit $check cell names as labels
2025-01-30 14:18:02 +00:00
Akash Levy
f403256a34
Merge branch 'YosysHQ:main' into main
2025-01-23 14:06:16 -08:00
