3556 commits

Author	SHA1	Message	Date
Clifford Wolf	00d32eb73d	Merge pull request #999 from jakobwenzel/setundefInitFix ... initialize more registers in setundef -init	2019-06-05 09:50:15 +02:00
Clifford Wolf	4190d7c094	Fix typo in fmcombine log message, fixes #1063 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-06-05 09:26:44 +02:00
Clifford Wolf	8a6f9977f6	Suppress driver-driver conflict warning for unknown cell types, fixes #1065 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-06-05 09:14:12 +02:00
Eddie Hung	94a5f4e609	Rename shregmap -tech xilinx -> xilinx_dynamic	2019-06-04 14:34:36 -07:00
Eddie Hung	f81a0ed92e	Merge remote-tracking branch 'origin/master' into xc7mux	2019-06-03 23:07:08 -07:00
Eddie Hung	295bd8d0bf	Remove dupe	2019-06-03 12:32:20 -07:00
Eddie Hung	eb08e71bd1	Merge branch 'xaig' into xc7mux	2019-05-31 13:03:03 -07:00
Eddie Hung	a379234f56	Throw out unused code inherited from abc	2019-05-31 12:50:11 -07:00
Clifford Wolf	90ec2cda42	Fix "tee" handling of log_streams ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-05-31 09:28:51 +02:00
Eddie Hung	4a6b9af227	Fix spelling	2019-05-30 15:50:47 -07:00
Eddie Hung	a44fe3a632	Revert "Re-enable &dc2" ... This reverts commit 8c58c728a7.	2019-05-30 11:41:50 -07:00
Eddie Hung	0800846e73	Do not double count LUT1s	2019-05-30 11:32:14 -07:00
Eddie Hung	8c58c728a7	Re-enable &dc2	2019-05-30 00:42:41 -07:00
Eddie Hung	2560f92f29	Reduce -W to 160	2019-05-29 23:01:46 -07:00
Eddie Hung	854557814e	Erase all boxes before stitching	2019-05-29 19:17:36 -07:00
Eddie Hung	b955344ecd	Call &if with -W 250	2019-05-29 16:34:52 -07:00
Eddie Hung	ecaa7856e9	Add some debug to abc9	2019-05-29 15:21:41 -07:00
Clifford Wolf	349c47250a	Merge pull request #1049 from YosysHQ/clifford/fix1047 ... Do not use shiftmul peepopt pattern when mul result is truncated	2019-05-28 19:02:26 +02:00
Eddie Hung	cdedf51c32	From master	2019-05-28 09:37:50 -07:00
Eddie Hung	914074a07c	Update from master	2019-05-28 09:35:45 -07:00
Eddie Hung	ba9513b325	Merge remote-tracking branch 'origin/master' into xc7mux	2019-05-28 09:30:53 -07:00
Eddie Hung	4a76b425cc	Misspell	2019-05-28 08:44:59 -07:00
Clifford Wolf	cb285e4b87	Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-05-28 17:17:56 +02:00
Clifford Wolf	ba2185ead8	Refactor hierarchy wand/wor handling ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-05-28 16:43:25 +02:00
Bogdan Vukobratovic	29a78267d7	Fix the regression	2019-05-28 15:45:04 +02:00
Bogdan Vukobratovic	9a468f81c4	Optimizing DFFs whose initial value prevents their value from changing ... This is a proof of concept implementation that invokes SAT solver via Pass::call method.	2019-05-28 08:48:21 +02:00
Eddie Hung	89bd6b8504	If driver not found, use LUT2	2019-05-27 23:12:21 -07:00
Eddie Hung	4df37c77fd	Disconnect all ABC boxes too	2019-05-27 19:40:27 -07:00
Eddie Hung	75bd41eaeb	Parse without wideports	2019-05-27 12:22:05 -07:00
Eddie Hung	bf3b8d5e45	Remove mapped_mod when done	2019-05-27 12:19:21 -07:00
Eddie Hung	234156c01a	Instantiate cell type (from sym file) otherwise 'clean' warnings	2019-05-27 12:16:10 -07:00
Eddie Hung	03b289a851	Add 'cinput' and 'coutput' to symbols file for boxes	2019-05-27 11:38:52 -07:00
Stefan Biereigel	816082d5a1	Merge branch 'master' into wandwor	2019-05-27 19:07:46 +02:00
Stefan Biereigel	ed625a3102	move wand/wor resolution into hierarchy pass	2019-05-27 18:00:22 +02:00
Clifford Wolf	2a9c68e2d6	Merge pull request #1026 from YosysHQ/clifford/fix1023 ... Keep zero-width wires in opt_clean if and only if they are ports	2019-05-27 13:24:19 +02:00
Eddie Hung	3981eba999	ABC9 to call &sweep	2019-05-26 11:31:35 -07:00
Eddie Hung	086b6560b4	Typo	2019-05-26 03:17:20 -07:00
Eddie Hung	823153e418	Combine ABC_COMMAND_LUT	2019-05-26 02:47:06 -07:00
Eddie Hung	32a4c10c0d	Fix "a" extension	2019-05-26 02:44:36 -07:00
Eddie Hung	d4fb6cac7c	Revert enable check	2019-05-25 12:55:57 -07:00
Eddie Hung	822d0b7789	opt_rmdff to optimise even in presence of enable signal, even removing	2019-05-24 18:30:51 -07:00
Eddie Hung	0d66103cbb	Add comments	2019-05-24 16:33:10 -07:00
Eddie Hung	357b1de6bc	Resolve @cliffordwolf review, set even if !has_init	2019-05-24 16:15:22 -07:00
Eddie Hung	6ad09bfcea	Add &fraig and &mfs back	2019-05-24 15:10:18 -07:00
Eddie Hung	68359bcd6f	Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux	2019-05-23 13:37:53 -07:00
Eddie Hung	5ac7e38d0a	Fix spacing	2019-05-23 12:58:30 -07:00
Eddie Hung	50ed34a6d0	opt_rmdff to work on $dffe and $_DFFE_*	2019-05-23 11:26:18 -07:00
Clifford Wolf	e3f9ccf56d	Keep zero-width wires in opt_clean if and only if they are ports, fixes #1023 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-05-22 13:57:36 +02:00
Eddie Hung	fb09c6219b	Merge remote-tracking branch 'origin/master' into xc7mux	2019-05-21 14:21:00 -07:00
Clifford Wolf	c4b8575f43	Add "wreduce -keepdc", fixes #1016 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-05-20 15:36:13 +02:00