mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-25 10:05:33 +00:00
Code Activity

Do not double count LUT1s

Browse source
This commit is contained in:
Eddie Hung 2019-05-30 11:32:14 -07:00
parent fdfc18be91
commit 0800846e73
1 changed files with 0 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

1
passes/techmap/abc9.cc
View file

@ -670,7 +670,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
driver_lut);
}
cell_stats["$lut"]++;
}
else {
cell = module->addCell(remap_name(c->name), "$_NOT_");