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Add some debug to abc9
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@ -423,6 +423,21 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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Pass::call(design, stringf("write_xaiger -O -map %s/input.sym %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str()));
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#if 0
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std::string buffer = stringf("%s/%s", tempdir_name.c_str(), "input.xaig");
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std::ifstream ifs;
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ifs.open(buffer);
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if (ifs.fail())
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log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
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buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
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log_assert(!design->module("$__abc9__"));
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AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, false /* wideports */);
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reader.parse_xaiger();
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ifs.close();
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Pass::call(design, stringf("write_verilog -noexpr -norename %s/%s", tempdir_name.c_str(), "input.v"));
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design->remove(design->module("$__abc9__"));
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#endif
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design->selection_stack.pop_back();
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// Now 'unexpose' those wires by undoing
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@ -540,9 +555,12 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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log_assert(!design->module("$__abc9__"));
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AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, false /* wideports */);
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reader.parse_xaiger();
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ifs.close();
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#if 0
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Pass::call(design, stringf("write_verilog -noexpr -norename %s/%s", tempdir_name.c_str(), "output.v"));
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#endif
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log_header(design, "Re-integrating ABC9 results.\n");
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RTLIL::Module *mapped_mod = design->module("$__abc9__");
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if (mapped_mod == NULL)
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