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Merge pull request #1026 from YosysHQ/clifford/fix1023

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Keep zero-width wires in opt_clean if and only if they are ports
This commit is contained in:
Clifford Wolf 2019-05-27 13:24:19 +02:00 • committed by GitHub
commit 2a9c68e2d6
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GPG key ID: 4AEE18F83AFDEB23
2 changed files with 12 additions and 2 deletions
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9
kernel/log.cc
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@ -230,6 +230,9 @@ static void logv_warning_with_prefix(const char *prefix,
}
else
{
int bak_log_make_debug = log_make_debug;
log_make_debug = 0;
for (auto &re : log_werror_regexes)
if (std::regex_search(message, re))
log_error("%s", message.c_str());
@ -254,6 +257,7 @@ static void logv_warning_with_prefix(const char *prefix,
}
log_warnings_count++;
log_make_debug = bak_log_make_debug;
}
}
@ -285,6 +289,9 @@ static void logv_error_with_prefix(const char *prefix,
#ifdef EMSCRIPTEN
auto backup_log_files = log_files;
#endif
int bak_log_make_debug = log_make_debug;
log_make_debug = 0;
log_suppressed();
if (log_errfile != NULL)
log_files.push_back(log_errfile);
@ -298,6 +305,8 @@ static void logv_error_with_prefix(const char *prefix,
log("%s%s", prefix, log_last_error.c_str());
log_flush();
log_make_debug = bak_log_make_debug;
if (log_error_atexit)
log_error_atexit();

5
passes/opt/opt_clean.cc
View file

@ -319,8 +319,9 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
wire->attributes.erase("\\init");
if (GetSize(wire) == 0) {
// delete zero-width wires
goto delete_this_wire;
// delete zero-width wires, unless they are module ports
if (wire->port_id == 0)
goto delete_this_wire;
} else
if (wire->port_id != 0 || wire->get_bool_attribute("\\keep") || !initval.is_fully_undef()) {
// do not delete anything with "keep" or module ports or initialized wires