mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-24 17:45:33 +00:00
Remove mapped_mod when done
This commit is contained in:
parent
234156c01a
commit
bf3b8d5e45
1 changed files with 2 additions and 0 deletions
|
@ -937,6 +937,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
|
|||
//log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
|
||||
log("ABC RESULTS: input signals: %8d\n", in_wires);
|
||||
log("ABC RESULTS: output signals: %8d\n", out_wires);
|
||||
|
||||
design->remove(mapped_mod);
|
||||
}
|
||||
//else
|
||||
//{
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue