mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-30 04:15:52 +00:00
Code Activity

Parse without wideports

Browse source
This commit is contained in:
Eddie Hung 2019-05-27 12:22:05 -07:00
parent bf3b8d5e45
commit 75bd41eaeb
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/techmap/abc9.cc
View file

@ -538,7 +538,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
//parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode);
buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
log_assert(!design->module("$__abc9__"));
AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, false /* wideports */);
reader.parse_xaiger();
ifs.close();