mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-11 03:33:36 +00:00
Code Activity

Misspell

Browse source
This commit is contained in:
Eddie Hung 2019-05-28 08:44:59 -07:00
parent 89bd6b8504
commit 4a76b425cc
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
passes/techmap/abc9.cc
View file

@ -567,7 +567,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
// Attempt another wideports_split here because there
// exists the possibility that different bits of a port
// could be an input and output, therefore parse_xiager()
// could be an input and output, therefore parse_xaiger()
// could not combine it into a wideport
auto r = wideports_split(w->name.str());
wire = module->wire(r.first);