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Author SHA1 Message Date
Krystine Sherwin
468a019c30
docs: Makefile tidying 
examples and dots are now orthogonal.
 2024-10-07 21:56:23 +13:00
Krystine Sherwin
2e1181a092
ci: Run make docs on PRs 2024-10-07 21:25:15 +13:00
github-actions[bot]
6155c59d00 Bump version 2024-10-07 00:21:37 +00:00
KrystalDelusion
3534e6b52d
Merge pull request #4632 from tarikgraba/main 
docs: avoid concurrency issues when generating images in parallel
 2024-10-07 10:33:02 +13:00
Krystine Sherwin
571d181fb4
Fix top-level make docs prerequisites 
Add `$(TARGETS)` for gen_examples and gen_images since they need the `yosys` executable.
Add guidelines source files as a prerequisite to docs/source/generated while we're at it.
 2024-10-07 10:26:29 +13:00
Krystine Sherwin
d8038c11d1
Add -j flag to make docs CI 2024-10-07 10:07:17 +13:00
TG
5841b44543 docs: Simplify images generation to allow parallel build 
- remove the tidy target from the main target.
  * aux/log file are already excluded in a .gititgnore file
  * allow parallel generation as the tidy target imposes sequential build
 2024-10-06 08:38:16 +02:00
Akash Levy
db55bbaf81 Add Liberty tests to test suite 2024-10-05 01:35:12 -10:00
Akash Levy
f76cb43ac7 Add bundle support 2024-10-05 01:35:03 -10:00
Akash Levy
36e57017fe Add Liberty to verilog conversion tests 2024-10-05 01:34:12 -10:00
Akash Levy
4de5e718ed Add two new Liberty test cases 2024-10-05 01:33:56 -10:00
Lofty
13ecbd5c76 quicklogic: test that dividing by a constant does not infer carry chains 2024-10-03 20:05:28 +01:00
Akash Levy
654e92e04e Fix Liberty issue 2024-10-03 04:14:20 -07:00
Akash Levy
dd487ca8a1 Updating Yosys 2024-10-03 01:46:09 -07:00
Akash Levy
5038bfa2af Fix minor whitespace thing 2024-10-03 00:29:16 -07:00
Akash Levy
195fff098b Small updates 2024-10-03 00:19:11 -07:00
Akash Levy
2d8588f15b Update Verific 2024-10-02 23:09:36 -07:00
Akash Levy
bc317a3930 Update deps 2024-10-02 22:19:14 -07:00
Akash Levy
ec296736f5 Simplify multiport 2024-10-02 22:19:09 -07:00
Akash Levy
e8d9622a59 wreduce test works now 2024-10-02 17:25:57 -07:00
Akash Levy
03f76bbddd Remove comments 2024-10-02 16:59:01 -07:00
Akash Levy
dd7e302aaa Revert wreduce 2024-10-02 03:55:19 -07:00
Akash Levy
400ae0bbab Prune RAM dimensions 2024-10-02 03:44:57 -07:00
Akash Levy
8bf86e8d1f Undo 2024-10-02 03:30:30 -07:00
Roland Coeurjoly
5ea2c6e6e5 Assume x values for missing signal data in FST 
Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-10-02 12:08:48 +02:00
Martin Povišer
ec42b42bd9 cellmatch: Size the lut attribute 2024-10-02 11:29:54 +02:00
Akash Levy
ff0fd570d8 Revert mem but fix Verific frontend to remove ugliness 2024-10-02 01:17:01 -07:00
Akash Levy
afe3b18a04 Another try on mem fix 2024-10-01 21:57:59 -07:00
Akash Levy
73902607cd Smallfix test 2024-10-01 07:46:56 -07:00
Akash Levy
af10f5e4f6 Update 2024-10-01 04:40:49 -07:00
Emil J. Tywoniak
997cb30f1f cxxrtl: test stream operator 2024-10-01 13:25:07 +02:00
Akash Levy
a0ebd9545a Try again 2024-10-01 04:13:01 -07:00
Akash Levy
3b8bc8098f Smallfix 2024-10-01 04:03:45 -07:00
Akash Levy
16b1eb1699 Update fix 2024-10-01 03:42:32 -07:00
Roland Coeurjoly
76c615b2ae Fix: handle VCD variable references with and without whitespace 
Co-authored-by: Miodrag Milanović <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-10-01 11:51:20 +02:00
Akash Levy
dd9687fc4c Add way to disable memory init 2024-10-01 01:32:29 -07:00
Akash Levy
776661ab40 Update dep 2024-09-30 18:59:44 -07:00
Akash Levy
7442bfaa2f
Merge branch 'YosysHQ:main' into main 2024-09-30 18:58:14 -07:00
github-actions[bot]
1bf908dea8 Bump version 2024-10-01 00:23:05 +00:00
Miodrag Milanović
500db6acc6
Merge pull request #4621 from RCoeurjoly/roland/get_vcd2fst 
Add "Get vcd2fst" step to test-yosys job
 2024-09-30 21:38:39 +02:00
Mohamed Gaber
35c8ad61ac
cli/python: error-checking, python interpreter bugfix 
* Less brittle method of adding script dirname to sys.path
* Check if scriptfp successfully opens before using it
* Move `log_error` to after `PyErr_Print()` is called
 2024-09-30 17:38:43 +03:00
Roland Coeurjoly
5fca9b867d Add Get vcd2fst step to test-yosys job 
Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-09-30 16:25:32 +02:00
Akash Levy
e21d007791 Bump dep version 2024-09-30 02:54:46 -07:00
Akash Levy
ee0b083a1e
Merge branch 'YosysHQ:main' into main 2024-09-30 02:43:09 -07:00
github-actions[bot]
59404f8ce5 Bump version 2024-09-30 00:21:26 +00:00
rherveille
ce7db661a8
Added cast to type support (#4284) 2024-09-29 17:03:01 -04:00
Akash Levy
599cebfca5 Include pmuxtree 2024-09-29 05:31:51 -07:00
Akash Levy
49d948d873 Fix splitfanout: keep original cell, add new cells to driver db to fix net messup 2024-09-29 03:07:07 -07:00
Akash Levy
9ecb4e798e Update deps 2024-09-28 19:49:07 -07:00
Akash Levy
0610d6ccc2 Smallfix to get GHDL working 2024-09-27 06:38:42 -07:00