mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-22 08:35:32 +00:00
Code Activity

Update

Browse source
This commit is contained in:
Akash Levy 2024-10-01 04:40:49 -07:00
parent a0ebd9545a
commit af10f5e4f6
2 changed files with 6 additions and 15 deletions
Download patch file Download diff file Expand all files Collapse all files

7
Makefile
View file

@ -8,9 +8,6 @@ CONFIG := none
# CONFIG := msys2-32
# CONFIG := msys2-64
# silimate
DISABLE_MEM_PRIORITY_MASK := 1 # not logically equivalent!
# features (the more the better)
ENABLE_TCL := 0
ENABLE_ABC := 0
@ -491,10 +488,6 @@ endif
endif
endif
ifeq ($(DISABLE_MEM_PRIORITY_MASK),1)
CXXFLAGS += -DSILIMATE_DISABLE_MEM_PRIORITY_MASK
endif
ifeq ($(ENABLE_GHDL),1)
GHDL_PREFIX ?= $(PREFIX)
GHDL_INCLUDE_DIR ?= $(GHDL_PREFIX)/include

14
kernel/mem.cc
View file

@ -782,14 +782,12 @@ namespace {
mwr.en = cell->getPort(ID::WR_EN).extract(i * res.width, (ni - i) * res.width);
mwr.addr = cell->getPort(ID::WR_ADDR).extract(i * abits, abits);
mwr.data = cell->getPort(ID::WR_DATA).extract(i * res.width, (ni - i) * res.width);
#ifndef SILIMATE_DISABLE_MEM_PRIORITY_MASK
if (!is_compat) {
Const priority_mask = cell->parameters.at(ID::WR_PRIORITY_MASK).extract(i * n_wr_ports, n_wr_ports);
for (int j = 0; j < n_wr_ports; j++)
if (wr_wide_continuation[j] != State::S1)
mwr.priority_mask.push_back(priority_mask[j] == State::S1);
}
#endif
// if (!is_compat) {
// Const priority_mask = cell->parameters.at(ID::WR_PRIORITY_MASK).extract(i * n_wr_ports, n_wr_ports);
// for (int j = 0; j < n_wr_ports; j++)
// if (wr_wide_continuation[j] != State::S1)
// mwr.priority_mask.push_back(priority_mask[j] == State::S1);
// }
res.wr_ports.push_back(mwr);
}
if (is_compat) {