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Add way to disable memory init

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This commit is contained in:
Akash Levy 2024-10-01 01:32:29 -07:00
parent 776661ab40
commit dd9687fc4c
2 changed files with 10 additions and 1 deletions
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9
Makefile
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@ -8,6 +8,10 @@ CONFIG := none
# CONFIG := msys2-32
# CONFIG := msys2-64
# silimate features and settings
ENABLE_SLANG := 1
DISABLE_MEM_INIT := 1 # does not preserve logic equivalence!
# features (the more the better)
ENABLE_TCL := 0
ENABLE_ABC := 0
@ -16,7 +20,6 @@ ENABLE_PLUGINS := 0
ENABLE_READLINE := 0
ENABLE_EDITLINE := 1
ENABLE_GHDL := 0
ENABLE_SLANG := 1
ENABLE_VERIFIC := 1
ENABLE_VERIFIC_SYSTEMVERILOG := 1
ENABLE_VERIFIC_VHDL := 0
@ -488,6 +491,10 @@ endif
endif
endif
ifeq ($(DISABLE_MEM_INIT),1)
CXXFLAGS += -DSILIMATE_DISABLE_MEM_INIT
endif
ifeq ($(ENABLE_GHDL),1)
GHDL_PREFIX ?= $(PREFIX)
GHDL_INCLUDE_DIR ?= $(GHDL_PREFIX)/include

2
kernel/mem.cc
View file

@ -703,6 +703,7 @@ namespace {
res.packed = true;
res.cell = cell;
res.attributes = cell->attributes;
#ifndef SILIMATE_DISABLE_MEM_INIT
Const &init = cell->parameters.at(ID::INIT);
if (!init.is_fully_undef()) {
int pos = 0;
@ -726,6 +727,7 @@ namespace {
}
}
}
#endif
int n_rd_ports = cell->parameters.at(ID::RD_PORTS).as_int();
int n_wr_ports = cell->parameters.at(ID::WR_PORTS).as_int();
Const rd_wide_continuation = is_compat ? Const(State::S0, n_rd_ports) : cell->parameters.at(ID::RD_WIDE_CONTINUATION);