4501 commits

Author	SHA1	Message	Date
Akash Levy	c58a50f880	Merge upstream	2025-01-21 04:36:34 -08:00
Peter Gadfort	66545caa1b	Merge branch 'main' into synth-flatten	2025-01-20 10:24:38 -07:00
Peter Gadfort	f0860459ac	add support for using scratchpad value for flatten.separator in flatten command	2025-01-18 10:45:19 -07:00
Akash Levy	d8631420a1	Add -nocells option to equiv_make and equiv_opt to ensure that equivalence is only checked for wires	2025-01-16 19:35:22 -08:00
Akash Levy	c42fd5164c	wreduce already swaps names no need for any diff	2025-01-16 19:34:41 -08:00
Alain Dargelas	2c359f4b58	Fix equiv_opt	2025-01-16 11:31:27 -08:00
Alain Dargelas	088683048b	Muxpack does not need splitfanout	2025-01-16 11:16:03 -08:00
N. Engelhardt	a5ba1d2eba	fix bugs in handling last id in hdlname to scopename conversion	2025-01-16 12:57:08 +01:00
Akash Levy	ee7975e4eb	Smallfix	2025-01-15 17:33:39 -08:00
Akash Levy	ec7b4b74b4	Use our naming convention instead of Yosys'	2025-01-15 17:09:26 -08:00
Alain Dargelas	31a5197a1c	muxadd and muldiv_c peepopt	2025-01-15 16:57:19 -08:00
N. Engelhardt	d640157ec4	fix some cases of hdlname being added to objects with private names	2025-01-15 15:56:42 +01:00
Akash Levy	b545fc4728	Reduce submod verbosity	2025-01-15 02:20:03 -08:00
Alain Dargelas	97928493e5	Fix assert	2025-01-14 11:57:03 -08:00
Alain Dargelas	d13c70c3c8	Wire rename	2025-01-14 10:03:54 -08:00
Alain Dargelas	14cfd027b7	opt_balance_tree pass formal equiv	2025-01-14 09:35:43 -08:00
Akash Levy	57bf3a6f51	Merge branch 'YosysHQ:main' into main	2025-01-14 08:38:59 -08:00
Emil J. Tywoniak	a58481e9b7	mark all hash_into methods nodiscard	2025-01-14 12:39:15 +01:00
Akash Levy	5c514e00a4	Sync with upstream	2025-01-13 17:20:59 -08:00
Martin Povišer	6225abec71	Merge pull request #4839 from mikesinouye/separator ... Add option for a custom flatten block separator char	2025-01-13 15:51:31 +01:00
Akash Levy	941d78a6ac	Make splitnetlist more efficient, no preliminary opt_clean in submod, remove $buf cells in opt_clean	2025-01-10 17:12:15 -08:00
Alain Dargelas	0f9901f128	forgot to recompute chains	2025-01-10 14:51:21 -08:00
Larry Doolittle	27be9a6b77	keep_hierarchy.cc: use strictly correct syntax for printf of uint64_t values ... Removes two warnings from the compile, at least on amd64 arch	2025-01-10 14:03:09 -08:00
Alain Dargelas	2ae521bbd1	Built-in splitfanout in muxpack	2025-01-10 13:55:23 -08:00
Alain Dargelas	99afdfa2bf	Merge branch 'main' into make_excl	2025-01-10 13:50:59 -08:00
Akash Levy	60d7723a64	Smallfixes to reconstruct busses to use logger and ignore blackboxes	2025-01-10 11:50:59 -08:00
Akash Levy	2b4e175698	bufnorm log_debug to reduce time	2025-01-09 19:24:54 -08:00
mikesinouye	13b183c9c5	Add option for a custom flatten block separator char	2025-01-09 18:30:23 -08:00
Martin Povišer	ca0ace66bc	Merge pull request #4817 from povik/macc_v2-1 ... macc: Stop using the B port	2025-01-08 14:42:51 +01:00
Martin Povišer	366e3f22fb	Merge pull request #4836 from YosysHQ/emil/share-fix-log ... share: fix misleading 0 cells log message	2025-01-08 13:14:34 +01:00
Martin Povišer	652a1b9806	macc: Stop using the B port ... The B port is for single-bit summands. These can just as well be represented as an additional summand on the A port (which supports summands of arbitrary width). An upcoming `$macc_v2` cell won't be special-casing single-bit summands in any way. In preparation, make the following changes: * remove the `bit_ports` field from the `Macc` helper (instead add any single-bit summands to `ports` next to other summands) * leave `B` empty on cells emitted from `Macc::to_cell`	2025-01-08 13:03:35 +01:00
Emil J. Tywoniak	1836a571c9	share: fix misleading log message	2025-01-07 19:25:15 +01:00
Akash Levy	2cf97cf744	Splitfanout index fix	2025-01-07 01:51:00 -08:00
Akash Levy	443613da69	Merge branch 'YosysHQ:main' into main	2025-01-07 00:56:19 -05:00
Martin Povišer	41e4aa8f0a	Merge pull request #4819 from povik/wreduce-resign ... wreduce: Optimize signedness when possible	2025-01-06 15:27:55 +01:00
Martin Povišer	be351886a5	wreduce: Adjust naming and comments	2025-01-03 12:54:34 +01:00
Alain Dargelas	fad1b285df	format	2024-12-30 17:25:06 -08:00
Alain Dargelas	0d5d7809f8	format	2024-12-30 17:24:06 -08:00
Alain Dargelas	11c9331a51	format	2024-12-30 17:23:00 -08:00
Alain Dargelas	163b1653b1	format	2024-12-30 17:17:47 -08:00
Alain Dargelas	af248c3cb2	format	2024-12-30 17:16:47 -08:00
Alain Dargelas	a32a7b27bc	format	2024-12-30 17:13:00 -08:00
Alain Dargelas	ad80b5336d	format	2024-12-30 17:08:07 -08:00
Alain Dargelas	8d6a542a5d	Decode logic for muxpack	2024-12-27 15:23:25 -08:00
Akash Levy	bb91c5c9da	Merge pull request #37 from alaindargelas/opt_balance_tree_fanout_limit ... New -limit_fanout option for opt_balance_tree	2024-12-20 14:05:22 -08:00
Akash Levy	1dcf75d175	Sync	2024-12-19 21:40:30 -08:00
Alain Dargelas	ab0058a568	New -limit_fanout option for opt_balance_tree	2024-12-19 11:44:39 -08:00
Emil J. Tywoniak	b9b9515bb0	hashlib: hash_eat -> hash_into	2024-12-18 15:09:25 +01:00
Emil J. Tywoniak	4e29ec1854	hashlib: acc -> eat	2024-12-18 15:09:25 +01:00
Emil J. Tywoniak	c73c88033d	hashlib: only include in one place	2024-12-18 14:58:31 +01:00