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https://github.com/YosysHQ/yosys
synced 2025-10-31 03:32:29 +00:00
New -limit_fanout option for opt_balance_tree
This commit is contained in:
Alain Dargelas
parent
56130cb5ec
commit
ab0058a568
1 changed files with 135 additions and 46 deletions
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@ -19,30 +19,35 @@
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/yosys.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct OptBalanceTreeWorker {
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// Module and signal map
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Design *design;
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Module *module;
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SigMap sigmap;
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bool allow_off_chain;
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int limit = -1;
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// Counts of each cell type that are getting balanced
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dict<IdString, int> cell_count;
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// Driver data
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dict<SigBit, tuple<IdString, IdString, int>> bit_drivers_db;
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// Load data
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dict<SigBit, pool<tuple<IdString, IdString, int>>> bit_users_db;
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// Signal chain data structures
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dict<SigSpec, Cell*> sig_chain_next;
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dict<SigSpec, Cell*> sig_chain_prev;
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dict<SigSpec, Cell *> sig_chain_next;
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dict<SigSpec, Cell *> sig_chain_prev;
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pool<SigBit> sigbit_with_non_chain_users;
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pool<Cell*> chain_start_cells;
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pool<Cell*> candidate_cells;
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pool<Cell *> chain_start_cells;
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pool<Cell *> candidate_cells;
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void make_sig_chain_next_prev(IdString cell_type) {
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void make_sig_chain_next_prev(IdString cell_type)
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{
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// Mark all wires with keep attribute as having non-chain users
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for (auto wire : module->wires()) {
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if (wire->get_bool_attribute(ID::keep)) {
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@ -59,14 +64,16 @@ struct OptBalanceTreeWorker {
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SigSpec a_sig = sigmap(cell->getPort(ID::A));
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SigSpec b_sig = sigmap(cell->getPort(ID::B));
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SigSpec y_sig = sigmap(cell->getPort(ID::Y));
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// If a_sig already has a chain user, mark its bits as having non-chain users
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// If a_sig already has a chain user, mark its bits as having non-chain users
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if (sig_chain_next.count(a_sig))
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for (auto a_bit : a_sig.bits())
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sigbit_with_non_chain_users.insert(a_bit);
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// Otherwise, mark cell as the next in the chain relative to a_sig
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else {
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sig_chain_next[a_sig] = cell;
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if (fanout_in_range(y_sig)) {
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sig_chain_next[a_sig] = cell;
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}
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}
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if (!b_sig.empty()) {
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@ -76,15 +83,19 @@ struct OptBalanceTreeWorker {
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sigbit_with_non_chain_users.insert(b_bit);
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// Otherwise, mark cell as the next in the chain relative to b_sig
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else {
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sig_chain_next[b_sig] = cell;
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if (fanout_in_range(y_sig)) {
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sig_chain_next[b_sig] = cell;
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}
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}
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}
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// Add cell as candidate
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candidate_cells.insert(cell);
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// Mark cell as the previous in the chain relative to y_sig
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sig_chain_prev[y_sig] = cell;
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if (fanout_in_range(y_sig)) {
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// Add cell as candidate
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candidate_cells.insert(cell);
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// Mark cell as the previous in the chain relative to y_sig
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sig_chain_prev[y_sig] = cell;
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}
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}
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// If cell is not matching type, mark all cell input signals as being non-chain users
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else {
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@ -96,7 +107,8 @@ struct OptBalanceTreeWorker {
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}
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}
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void find_chain_start_cells() {
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void find_chain_start_cells()
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{
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for (auto cell : candidate_cells) {
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// Log candidate cell
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log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type));
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@ -105,7 +117,7 @@ struct OptBalanceTreeWorker {
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SigSpec a_sig = sigmap(cell->getPort(ID::A));
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SigSpec b_sig = sigmap(cell->getPort(ID::B));
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SigSpec prev_sig = sig_chain_prev.count(a_sig) ? a_sig : b_sig;
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// This is a start cell if there was no previous cell in the chain for a_sig or b_sig
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if (sig_chain_prev.count(a_sig) + sig_chain_prev.count(b_sig) != 1) {
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chain_start_cells.insert(cell);
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@ -121,9 +133,10 @@ struct OptBalanceTreeWorker {
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}
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}
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vector<Cell*> create_chain(Cell *start_cell) {
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vector<Cell *> create_chain(Cell *start_cell)
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{
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// Chain of cells
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vector<Cell*> chain;
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vector<Cell *> chain;
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// Current cell
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Cell *c = start_cell;
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@ -146,7 +159,8 @@ struct OptBalanceTreeWorker {
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return chain;
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}
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void wreduce(Cell *cell) {
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void wreduce(Cell *cell)
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{
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// If cell is arithmetic, remove leading zeros from inputs, then clean up outputs
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if (cell->type.in(ID($add), ID($mul))) {
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// Remove leading zeros from inputs
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@ -158,13 +172,14 @@ struct OptBalanceTreeWorker {
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SigSpec inport_sig = sigmap(cell->getPort(inport));
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cell->unsetPort(inport);
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if (cell->getParam((inport == ID::A) ? ID::A_SIGNED : ID::B_SIGNED).as_bool()) {
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while (GetSize(inport_sig) > 1 && inport_sig[GetSize(inport_sig)-1] == State::S0 && inport_sig[GetSize(inport_sig)-2] == State::S0) {
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inport_sig.remove(GetSize(inport_sig)-1, 1);
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while (GetSize(inport_sig) > 1 && inport_sig[GetSize(inport_sig) - 1] == State::S0 &&
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inport_sig[GetSize(inport_sig) - 2] == State::S0) {
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inport_sig.remove(GetSize(inport_sig) - 1, 1);
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bits_removed++;
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}
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} else {
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while (GetSize(inport_sig) > 0 && inport_sig[GetSize(inport_sig)-1] == State::S0) {
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inport_sig.remove(GetSize(inport_sig)-1, 1);
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while (GetSize(inport_sig) > 0 && inport_sig[GetSize(inport_sig) - 1] == State::S0) {
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inport_sig.remove(GetSize(inport_sig) - 1, 1);
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bits_removed++;
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}
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}
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@ -184,7 +199,8 @@ struct OptBalanceTreeWorker {
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width = std::max(cell->getParam(ID::A_WIDTH).as_int(), cell->getParam(ID::B_WIDTH).as_int()) + 1;
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else if (cell->type == ID($mul))
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width = cell->getParam(ID::A_WIDTH).as_int() + cell->getParam(ID::B_WIDTH).as_int();
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else log_abort();
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else
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log_abort();
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for (int i = GetSize(y_sig) - 1; i >= width; i--) {
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module->connect(y_sig[i], State::S0);
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y_sig.remove(i, 1);
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@ -198,7 +214,8 @@ struct OptBalanceTreeWorker {
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cell->fixup_parameters();
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}
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void process_chain(vector<Cell*> &chain) {
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void process_chain(vector<Cell *> &chain)
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{
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// If chain size is less than 3, no balancing needed
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if (GetSize(chain) < 3)
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return;
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@ -208,8 +225,8 @@ struct OptBalanceTreeWorker {
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Cell *cell = mid_cell; // SILIMATE: Set cell to mid_cell for better naming
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Cell *midnext_cell = chain[GetSize(chain) / 2 + 1];
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Cell *end_cell = chain.back();
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log_debug("Balancing chain of %d cells: mid=%s, midnext=%s, endcell=%s\n",
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GetSize(chain), log_id(mid_cell), log_id(midnext_cell), log_id(end_cell));
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log_debug("Balancing chain of %d cells: mid=%s, midnext=%s, endcell=%s\n", GetSize(chain), log_id(mid_cell), log_id(midnext_cell),
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log_id(end_cell));
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// Get mid signals
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SigSpec mid_a_sig = sigmap(mid_cell->getPort(ID::A));
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@ -238,17 +255,17 @@ struct OptBalanceTreeWorker {
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sigmap.set(module);
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// Get subtrees
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vector<Cell*> left_chain(chain.begin(), chain.begin() + GetSize(chain) / 2);
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vector<Cell*> right_chain(chain.begin() + GetSize(chain) / 2 + 1, chain.end());
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vector<Cell *> left_chain(chain.begin(), chain.begin() + GetSize(chain) / 2);
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vector<Cell *> right_chain(chain.begin() + GetSize(chain) / 2 + 1, chain.end());
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// Recurse on subtrees
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process_chain(left_chain);
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process_chain(right_chain);
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// Width reduce left subtree
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for (auto c : left_chain)
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wreduce(c);
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// Width reduce right subtree
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for (auto c : right_chain)
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wreduce(c);
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@ -260,7 +277,8 @@ struct OptBalanceTreeWorker {
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wreduce(mid_cell);
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}
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void cleanup() {
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void cleanup()
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{
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// Fix ports
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module->fixup_ports();
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@ -272,10 +290,74 @@ struct OptBalanceTreeWorker {
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candidate_cells.clear();
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}
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OptBalanceTreeWorker(Design* design, Module *module, const vector<IdString> cell_types, bool allow_off_chain) :
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design(design), module(module), sigmap(module), allow_off_chain(allow_off_chain) {
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bool fanout_in_range(SigSpec outsig)
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{
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// Check if output signal is "bit-split", skip if so
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// This is a lookahead for the splitfanout pass that has this limitation
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auto bit_users = bit_users_db[outsig[0]];
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for (int i = 0; i < GetSize(outsig); i++) {
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if (bit_users_db[outsig[i]] != bit_users) {
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return false;
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}
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}
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// Skip if fanout is above limit
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if (limit != -1 && GetSize(bit_users) > limit) {
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return false;
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}
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return true;
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}
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OptBalanceTreeWorker(Design *design, Module *module, const vector<IdString> cell_types, bool allow_off_chain, int limit)
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: design(design), module(module), sigmap(module), allow_off_chain(allow_off_chain), limit(limit)
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{
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if (allow_off_chain) {
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// Build bit_drivers_db
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log("Building bit_drivers_db...\n");
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for (auto cell : module->cells()) {
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for (auto conn : cell->connections()) {
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if (!cell->output(conn.first))
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continue;
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for (int i = 0; i < GetSize(conn.second); i++) {
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SigBit bit(sigmap(conn.second[i]));
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bit_drivers_db[bit] = tuple<IdString, IdString, int>(cell->name, conn.first, i);
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}
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}
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}
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// Build bit_users_db
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log("Building bit_users_db...\n");
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for (auto cell : module->cells()) {
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for (auto conn : cell->connections()) {
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if (!cell->input(conn.first))
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continue;
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for (int i = 0; i < GetSize(conn.second); i++) {
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SigBit bit(sigmap(conn.second[i]));
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if (!bit_drivers_db.count(bit))
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continue;
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bit_users_db[bit].insert(
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tuple<IdString, IdString, int>(cell->name, conn.first, i - std::get<2>(bit_drivers_db[bit])));
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}
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}
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}
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// Build bit_users_db for output ports
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log("Building bit_users_db for output ports...\n");
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for (auto wire : module->wires()) {
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if (!wire->port_output)
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continue;
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SigSpec sig(sigmap(wire));
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for (int i = 0; i < GetSize(sig); i++) {
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SigBit bit(sig[i]);
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if (!bit_drivers_db.count(bit))
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continue;
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bit_users_db[bit].insert(
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tuple<IdString, IdString, int>(wire->name, IdString(), i - std::get<2>(bit_drivers_db[bit])));
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}
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}
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// Deselect all cells
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Pass::call(design, "select -none");
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// Do for each cell type
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@ -308,7 +390,7 @@ struct OptBalanceTreeWorker {
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sigmap.set(module);
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}
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// Do for each cell type
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// Do for each cell type
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for (auto cell_type : cell_types) {
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// Find chains of ops
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make_sig_chain_next_prev(cell_type);
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@ -316,7 +398,7 @@ struct OptBalanceTreeWorker {
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// For each chain, if len >= 3, convert to tree via "rotation" and recurse on subtrees
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for (auto c : chain_start_cells) {
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vector<Cell*> chain = create_chain(c);
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vector<Cell *> chain = create_chain(c);
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process_chain(chain);
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cell_count[cell_type] += GetSize(chain);
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}
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@ -328,8 +410,9 @@ struct OptBalanceTreeWorker {
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};
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struct OptBalanceTreePass : public Pass {
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OptBalanceTreePass() : Pass("opt_balance_tree", "$and/$or/$xor/$xnor/$add/$mul cascades to trees") { }
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void help() override {
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OptBalanceTreePass() : Pass("opt_balance_tree", "$and/$or/$xor/$xnor/$add/$mul cascades to trees") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_balance_tree [options] [selection]\n");
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@ -341,20 +424,26 @@ struct OptBalanceTreePass : public Pass {
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log(" Allows matching of cells that have loads outside the chain. These cells\n");
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log(" will be replicated and balanced into a tree, but the original\n");
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log(" cell will remain, driving its original loads.\n");
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log(" -fanout_limit n\n");
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log(" max fanout to split.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override {
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing OPT_BALANCE_TREE pass (cell cascades to trees).\n");
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bool allow_off_chain = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-allow-off-chain")
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{
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int limit = -1;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-allow-off-chain") {
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allow_off_chain = true;
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continue;
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}
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if (args[argidx] == "-fanout_limit" && argidx + 1 < args.size()) {
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limit = std::stoi(args[++argidx]);
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -363,7 +452,7 @@ struct OptBalanceTreePass : public Pass {
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dict<IdString, int> cell_count;
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const vector<IdString> cell_types = {ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul)};
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for (auto module : design->selected_modules()) {
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OptBalanceTreeWorker worker(design, module, cell_types, allow_off_chain);
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OptBalanceTreeWorker worker(design, module, cell_types, allow_off_chain, limit);
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for (auto cell : worker.cell_count) {
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cell_count[cell.first] += cell.second;
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}
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