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Wire rename

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This commit is contained in:
Alain Dargelas 2025-01-14 10:03:54 -08:00
parent 14cfd027b7
commit d13c70c3c8
1 changed files with 9 additions and 3 deletions
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12
passes/opt/opt_balance_tree.cc
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@ -405,10 +405,16 @@ struct OptBalanceTreeWorker {
for (auto c : chain_start_cells) {
vector<Cell *> chain = create_chain(c);
if (process_chain(chain)) {
// Rename cells for formal check to pass as cells signals have changed functionalities post rotation
// Rename cells and wires for formal check to pass as cells signals have changed functionalities post rotation
for (Cell *cell : chain) {
module->rename(cell, NEW_ID2_SUFFIX("mid_cell"));
log("Renaming cell %s \n", cell->name.c_str());
module->rename(cell, NEW_ID2_SUFFIX("rot_cell"));
}
for (Cell *cell : chain) {
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
Wire *wire = y_sig.as_wire();
if (wire && !wire->port_input && !wire->port_output) {
module->rename(y_sig.as_wire(), NEW_ID2_SUFFIX("rot_wire"));
}
}
}
cell_count[cell_type] += GetSize(chain);