mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-21 16:16:39 +00:00
Code Activity

Make splitnetlist more efficient, no preliminary opt_clean in submod, remove $buf cells in opt_clean

Browse source
This commit is contained in:
Akash Levy 2025-01-10 17:12:15 -08:00
parent a83e5f46d0
commit 941d78a6ac
3 changed files with 3 additions and 11 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
passes/cmds/splitnetlist.cc
View file

@ -161,10 +161,6 @@ struct SplitNetlist : public ScriptPass {
log("Running splitnetlist pass\n");
log_flush();
// Add buffers for pass-through and connections to constants
// so we can find cells that can be used by submod
Pass::call(design, "bufnorm -buf");
if (debug)
run_pass("write_rtlil post_buf.rtlil");
@ -268,10 +264,6 @@ struct SplitNetlist : public ScriptPass {
// Execute the submod command
Pass::call(design, "submod");
// Remove buffers introduced by bufnorm
Pass::call(design, "techmap -D SIMLIB_NOCHECKS -map +/simlib.v t:$buf");
Pass::call(design, "clean");
log("End splitnetlist pass\n");
log_flush();
}

4
passes/hierarchy/submod.cc
View file

@ -381,8 +381,8 @@ struct SubmodPass : public Pass {
if (opt_name.empty())
{
Pass::call(design, "opt_clean");
log_header(design, "Continuing SUBMOD pass.\n");
// Pass::call(design, "opt_clean");
// log_header(design, "Continuing SUBMOD pass.\n");
std::set<RTLIL::IdString> handled_modules;

2
passes/opt/opt_clean.cc
View file

@ -601,7 +601,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool unusedbitsattr
std::vector<RTLIL::Cell*> delcells;
for (auto cell : module->cells())
if (cell->type.in(ID($pos), ID($_BUF_)) && !cell->has_keep_attr()) {
if (cell->type.in(ID($pos), ID($_BUF_), ID($buf)) && !cell->has_keep_attr()) {
bool is_signed = cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool();
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec y = cell->getPort(ID::Y);