Krystine Sherwin
be05fae559
analogdevices: Extra tests
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`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
2026-01-27 00:25:08 +00:00
Lofty
9f9835e8e3
analogdevices: DSP inference
2026-01-27 00:25:08 +00:00
Krystine Sherwin
4d9ea44818
analogdevices: Update lutram.ys test
2026-01-27 00:25:08 +00:00
Lofty
4cdabf9376
test suite
2026-01-27 00:25:08 +00:00
Gus Smith
09ceadfde7
Merge pull request #4269 from povik/icells_not_derived
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Avoid `module_not_derived` on internal cells in techmap result
2026-01-26 14:48:40 -08:00
Emil J
5b10c7f3c6
Merge pull request #4928 from XutaxKamay/main
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Add gatesi_mode to init gates under gates_mode in BLIF format
2026-01-26 23:30:11 +01:00
Emil J
673c8d1ae7
Merge pull request #5615 from rocallahan/remove-used-signals-updates
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Don't update `used_signals` for retained wires in `rmunused_module_signals`.
2026-01-26 15:47:25 +01:00
Robert O'Callahan
32e96605d4
Don't update used_signals for retained wires in rmunused_module_signals.
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These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.
These updates will also make it difficult to process these wires in parallel.
2026-01-24 03:41:18 +00:00
Emil J
f5ea73eb97
Merge pull request #5557 from nataliakokoromyti/lut2mux-word
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lut2mux: add -word option
2026-01-23 17:24:41 +01:00
KrystalDelusion
125609105d
Merge pull request #5593 from RCoeurjoly/RCoeurjoly/5574_fix
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abc: handle ABC script errors instead of hanging
2026-01-23 07:16:48 +13:00
Emil J
317a4d77c7
Merge pull request #5610 from nataliakokoromyti/upstream-debugon
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Add debugon pass for persistent debug logging
2026-01-21 17:34:30 +01:00
Emil J
5e36503676
Merge pull request #5605 from nataliakokoromyti/opt_balance_tree
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Add opt_balance_tree pass
2026-01-21 17:34:08 +01:00
Gus Smith
491276983e
Add test
2026-01-19 18:34:55 -08:00
Krystine Sherwin
0f478a5952
tests/bug5574: Fix for non threaded abc
2026-01-20 05:56:14 +13:00
Natalia
ed64df737b
Add -on/-off modes to debug pass
2026-01-15 12:07:26 -08:00
Natalia
d5e1647d11
fix tests with truncation issues
2026-01-14 18:03:30 -08:00
Emil J. Tywoniak
ddf3c6c8b7
blif: add -gatesi test
2026-01-14 21:41:56 +01:00
nella
763001885f
Merge pull request #5608 from YosysHQ/nella/rtlil-to-string
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Add rtlil string getters
2026-01-14 19:00:47 +01:00
nella
210b733555
Add rtlil string getters
2026-01-14 15:37:18 +01:00
Natalia Kokoromyti
8b6925c5b0
Add opt_balance_tree pass for timing optimization
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This pass converts cascaded chains of arithmetic and logic cells ($add,
$mul, $and, $or, $xor) into balanced binary trees to improve timing
performance in hardware synthesis.
The optimization uses a breadth-first search approach to identify chains
of compatible cells, then recursively constructs balanced trees that
reduce the critical path depth.
Features:
- Supports arithmetic cells: $add, $mul
- Supports logic cells: $and, $or, $xor
- Command-line options: -arith (arithmetic only), -logic (logic only)
- Preserves signed/unsigned semantics
- Comprehensive test suite with 30 test cases
Original implementation by Akash Levy <akash@silimate.com> for Silimate.
Upstreamed from https://github.com/Silimate/yosys
2026-01-13 14:20:11 -08:00
Emil J
5ba0e9cae3
Merge pull request #4235 from ylm/genblk_wire
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Add autowires in genblk/for expension
2026-01-13 16:40:22 +01:00
nella
b332279baf
Merge pull request #5592 from YosysHQ/gus/5503-yw-load-error-msg
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More helpful error messages when loading Yosys Witness files with `yosys-smtbmc`
2026-01-13 12:00:06 +01:00
Emil J
cc25ccfcd7
Merge pull request #5559 from nataliakokoromyti/upstream-lut2bmux
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add lut2bmux
2026-01-12 16:09:13 +01:00
Robert O'Callahan
41a098172d
Expect an error from the bug5574.ys test
2026-01-08 09:58:01 +01:00
Roland Coeurjoly
f1fc704c84
abc: handle ABC script errors instead of hanging
2026-01-07 23:46:33 +01:00
Krystine Sherwin
9a09758f56
Test empty switches
2026-01-07 13:21:33 +13:00
Gus Smith
9f77465170
Add test
2026-01-06 16:19:04 -08:00
Emil J
0ab967b036
Merge pull request #5564 from rocallahan/pass-fuzz
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Add support for fuzz-test comparison of two passes intended to give identical RTLIL results
2026-01-06 20:07:31 +01:00
Emil J
2e1a2cfacb
Merge pull request #5561 from YosysHQ/emil/opt_expr-test-avoid-multiple-drivers
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opt_expr: avoid multiple drivers in test
2026-01-06 14:54:55 +01:00
Natalia
11b0e7ad92
add lut2bmux
2026-01-06 14:48:16 +01:00
Miodrag Milanović
d523c88c3c
Merge pull request #5573 from rocallahan/increase-timeout
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Increase test timeout to 10 seconds
2025-12-29 12:38:34 +01:00
Robert O'Callahan
99d7ab9c42
Increase test timeout to 10 seconds
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On my machine, this test regularly times out when doing "make -j" (which defaults to 128).
The high degree of parallelism seems to slow down the spwaning of ABC processes.
2025-12-29 04:35:05 +00:00
Natalia
721b504479
lut2mux: add -word option and test
2025-12-23 05:57:40 -08:00
Robert O'Callahan
9ee51c8f27
Add AFL++ Grammar-Generator grammar for RTLIL fuzzing, and instructions for how to use it.
2025-12-22 21:56:26 +00:00
Robert O'Callahan
914e14946d
Implement design_equal command
2025-12-21 21:47:40 +00:00
Emil J. Tywoniak
856d455065
opt_expr: avoid multiple drivers issue #4792 in combined assign tests
2025-12-19 18:32:56 +01:00
Emil J. Tywoniak
772d821fb0
opt_expr: reindent test
2025-12-19 18:32:56 +01:00
N. Engelhardt
45d654e2d7
avoid merging formal properties
2025-12-17 20:25:24 +01:00
Miodrag Milanović
d861a26e49
Merge pull request #5504 from nataliakokoromyti/verific-run-test-bugfix
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Fix Verific run-test.sh
2025-12-17 11:08:44 +01:00
nataliakokoromyti
2ded4bd893
Update run-test.sh
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fix: preserve newline at eof
2025-12-16 04:16:03 -08:00
Krystine Sherwin
c69be9d767
Missed an iverilog
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Should now still report an iverilog issue if `iverilog` doesn't exist.
2025-12-15 10:31:17 +13:00
Krystine Sherwin
24f4902156
Don't mention iverilog if the error wasn't from iverilog
2025-12-15 10:17:19 +13:00
Emil J
f003eca615
Merge pull request #5526 from YosysHQ/emil/fix-cellaigs-function-arg-eval-order
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cellaigs: fix function argument evaluation order
2025-12-12 10:00:09 +01:00
Krystine Sherwin
4da0c552dd
tests/aiger: Fix pipe hiding diff exit status
2025-12-12 11:26:24 +13:00
Yannick Lamarre
54b278d574
Add tests for implicit wires in generate blocks.
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Signed-off-by: Yannick Lamarre <yan.lamarre@gmail.com>
2025-12-10 14:43:42 +01:00
Emil J
e08e9119ee
Merge pull request #5516 from rocallahan/limit-threads
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Limit thread usage in tests
2025-12-10 13:45:07 +01:00
Emil J
46fbed6e6f
Merge pull request #5525 from YosysHQ/emil/fix-xaiger2-empty-cell-input
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aiger2: fix empty cell input
2025-12-04 16:47:53 +01:00
Robert O'Callahan
2ca28d964b
Limit YOSYS_MAX_THREADS to 4 for abcopt-tests
2025-12-04 12:09:49 +01:00
Robert O'Callahan
a871415abf
Limit YOSYS_MAX_THREADS to 4 when running seed-tests
2025-12-04 12:09:48 +01:00
Robert O'Callahan
fc951a28d3
Limit YOSYS_MAX_THREADS to 4 when running makefile-tests so we don't overload systems when running 'make -j... test'
2025-12-04 12:09:04 +01:00
