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Implement design_equal command

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Robert O'Callahan 2025-12-16 01:39:39 +00:00
parent 64a933d77b
commit 914e14946d
4 changed files with 392 additions and 0 deletions
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22
tests/various/design_equal_fail.ys Normal file
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logger -expect error "Second design missing module top_renamed" 1
read_rtlil <<EOT
module \top
wire width 1 input 1 \a
wire width 1 output 2 \y
connect \y \a
end
EOT
design -save golden
design -reset
read_rtlil <<EOT
module \top_renamed
wire width 1 input 1 \a
wire width 1 output 2 \y
connect \y \a
end
EOT
design_equal golden

17
tests/various/design_equal_pass.ys Normal file
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read_rtlil <<EOT
module \top
wire width 1 input 1 \a
wire width 1 output 2 \y
connect \y \a
end
EOT
design -save golden
design_equal golden
design -save copy
design_equal copy
design -load golden
design_equal golden
design_equal copy