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avoid merging formal properties

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N. Engelhardt 2025-12-17 20:25:24 +01:00
parent 49feaa1146
commit 45d654e2d7
4 changed files with 26 additions and 1 deletions
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16
tests/opt/opt_merge_properties.ys Normal file
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@ -0,0 +1,16 @@
read_verilog -sv <<EOF
module top ();
always_comb begin
label1: cover(0);
label2: cover(0);
end
endmodule
EOF
hierarchy -top top
proc
chformal -lower
clean
opt_merge
select -assert-count 2 t:$cover