mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-01-27 20:38:45 +00:00
Code Activity
16559 commits 117 branches 63 tags 61 MiB
Commit graph

16559 commits

This branch
This branch
All branches
Author SHA1 Message Date
Krystine Sherwin
be05fae559 analogdevices: Extra tests 
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
 2026-01-27 00:25:08 +00:00
Krystine Sherwin
92ebc2b4aa analogdevices: Fixing up bram 
Tested all the accepted configurations in eXpreso, disabling the RBRAM2 configs that fail to place, and increasing the cost for the double site TDP memories.
 2026-01-27 00:25:08 +00:00
Krystine Sherwin
3ee302fa6a analogdevices: Add BRAM options 
Enable `-force-params`, and tidy up lutram mapping too.
 2026-01-27 00:25:08 +00:00
Krystine Sherwin
8efcd811c3 memory_libmap: Add -force-params 
Reduce complexity for adi brams by unconditionally providing the WIDTH and ABITS parameters.
 2026-01-27 00:25:08 +00:00
Lofty
201b9f1cbb analogdevices: LUT RAM only on positive edge 2026-01-27 00:25:08 +00:00
Lofty
6554a34ccf analogdevices: DSP tweaks 2026-01-27 00:25:08 +00:00
Lofty
9f9835e8e3 analogdevices: DSP inference 2026-01-27 00:25:08 +00:00
Lofty
da2b6a5eb9 analogdevices: remove cells_xtra 2026-01-27 00:25:08 +00:00
Lofty
746bf7dc28 analogdevices: timings for t40lp 2026-01-27 00:25:08 +00:00
Lofty
90685470aa analogdevices: use single tech param 2026-01-27 00:25:08 +00:00
Lofty
3574a4e9f5 analogdevices: expreso does not care about clock buffers 2026-01-27 00:25:08 +00:00
Lofty
5228d4800a analogdevices: prepare for t40lp timings 2026-01-27 00:25:08 +00:00
Krystine Sherwin
88038614a0 analogdevices: Adding RBRAM2 and -tech 2026-01-27 00:25:08 +00:00
Krystine Sherwin
0e687bb42a analogdevices: (some) Native BRAM 
Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy).
Drop the unused defines from the synth pass.
Remove comments from the lutram files referencing xilinx.
 2026-01-27 00:25:08 +00:00
Krystine Sherwin
4d9ea44818 analogdevices: Update lutram.ys test 2026-01-27 00:25:08 +00:00
Krystine Sherwin
1dddec10cc analogdevices: Native LUTRAM primitives 2026-01-27 00:25:08 +00:00
Lofty
f5a223ecea analogdevices: LUTRAM config 2026-01-27 00:25:08 +00:00
Lofty
4e9451b19d analogdevices: update timing model 2026-01-27 00:25:08 +00:00
Lofty
d1cfa01570 I thought I removed this... 2026-01-27 00:25:08 +00:00
Lofty
cd64a4db76 analogdevices: user retargeting 2026-01-27 00:25:08 +00:00
Lofty
c2db4daeb9 analogdevices: more housekeeping 2026-01-27 00:25:08 +00:00
Lofty
839a974702 analogdevices: remove some extra cells! 2026-01-27 00:25:08 +00:00
Lofty
4cdabf9376 test suite 2026-01-27 00:25:08 +00:00
Lofty
0047b645d4 synth_analogdevices: remove scopeinfo cells 2026-01-27 00:25:08 +00:00
Lofty
bf602c5a72 Create synth_analogdevices 2026-01-27 00:25:08 +00:00
Gus Smith
09ceadfde7
Merge pull request #4269 from povik/icells_not_derived 
Avoid `module_not_derived` on internal cells in techmap result
 2026-01-26 14:48:40 -08:00
Emil J
5b10c7f3c6
Merge pull request #4928 from XutaxKamay/main 
Add gatesi_mode to init gates under gates_mode in BLIF format
 2026-01-26 23:30:11 +01:00
Emil J
29a9e42b64
Merge pull request #5628 from rocallahan/linux-perf-ctl 
Add `linux_perf` command to turn Linux perf recording on and off.
 2026-01-26 19:32:55 +01:00
Emil J
673c8d1ae7
Merge pull request #5615 from rocallahan/remove-used-signals-updates 
Don't update `used_signals` for retained wires in `rmunused_module_signals`.
 2026-01-26 15:47:25 +01:00
Robert O'Callahan
32e96605d4 Don't update used_signals for retained wires in rmunused_module_signals. 
These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.

These updates will also make it difficult to process these wires in parallel.
 2026-01-24 03:41:18 +00:00
Emil J
f5ea73eb97
Merge pull request #5557 from nataliakokoromyti/lut2mux-word 
lut2mux: add -word option
 2026-01-23 17:24:41 +01:00
Robert O'Callahan
4f53612725 Add linux_perf command to turn Linux perf recording on and off. 
This is extremely useful for profiling specific passes.
 2026-01-23 01:44:57 +00:00
KrystalDelusion
125609105d
Merge pull request #5593 from RCoeurjoly/RCoeurjoly/5574_fix 
abc: handle ABC script errors instead of hanging
 2026-01-23 07:16:48 +13:00
KrystalDelusion
98f848e503
Merge pull request #5546 from YosysHQ/krys/nested_packages 
Document nesting packages as unsupported
 2026-01-23 07:16:22 +13:00
github-actions[bot]
a6fc695522 Bump version 2026-01-22 00:28:34 +00:00
Emil J
317a4d77c7
Merge pull request #5610 from nataliakokoromyti/upstream-debugon 
Add debugon pass for persistent debug logging
 2026-01-21 17:34:30 +01:00
Emil J
5e36503676
Merge pull request #5605 from nataliakokoromyti/opt_balance_tree 
Add opt_balance_tree pass
 2026-01-21 17:34:08 +01:00
Miodrag Milanović
2157f9b3fb
Merge pull request #5622 from rocallahan/spurious-copy 
Avoid spurious copy in `IdStringCollector::trace_named()`
 2026-01-21 08:30:07 +01:00
Robert O'Callahan
2c0448a81b Avoid spurious copy in IdStringCollector::trace_named() 2026-01-21 03:31:56 +00:00
github-actions[bot]
57ac113b7f Bump version 2026-01-21 00:27:51 +00:00
Miodrag Milanović
bfd1401b32
Merge pull request #5612 from YosysHQ/sv2017 
verific: add explicit System Verilog 2017 option
 2026-01-20 14:44:46 +01:00
Miodrag Milanovic
d0fa4781c6 verific: Fix -sv2017 message and formatting 2026-01-20 08:07:26 +01:00
Gus Smith
491276983e Add test 2026-01-19 18:34:55 -08:00
Martin Povišer
90673cb0a2 techmap: Use -icells mode of frontend instead of type fixup 2026-01-19 16:49:49 -08:00
Martin Povišer
f67d4bcfa4 verilog: Do not set module_not_derived on internal cells 2026-01-19 16:48:13 -08:00
github-actions[bot]
49e5950791 Bump version 2026-01-20 00:26:10 +00:00
Krystine Sherwin
0f478a5952
tests/bug5574: Fix for non threaded abc 2026-01-20 05:56:14 +13:00
Miodrag Milanovic
cc3038f468 verific: Fix -sv2017 message 2026-01-19 16:32:46 +01:00
Miodrag Milanović
2bde91b6ef
Merge pull request #5618 from YosysHQ/update_abc 
Update ABC as per 2026-01-19
 2026-01-19 15:45:02 +01:00
nella
67d10a41e8
Merge pull request #5617 from YosysHQ/emil/consteval-description 
consteval: describe
 2026-01-19 14:56:24 +01:00