1755 commits

Author	SHA1	Message	Date
Clifford Wolf	81a9ee2360	Added handling of local memories and error for local decls in unnamed blocks	2017-01-04 16:03:04 +01:00
Clifford Wolf	dfb461fe52	Added Verilog $rtoi and $itor support	2017-01-03 17:40:58 +01:00
Clifford Wolf	3886669ab6	Added "verilog_defines" command	2016-12-15 17:49:28 +01:00
Clifford Wolf	ecdc22b06c	Added support for macros as include file names	2016-11-28 14:50:17 +01:00
Clifford Wolf	c7f6fb6e17	Bugfix in "read_verilog -D NAME=VAL" handling	2016-11-28 14:45:05 +01:00
Clifford Wolf	70d7a02cae	Added support for hierarchical defparams	2016-11-15 13:35:19 +01:00
Clifford Wolf	a926a6afc2	Remember global declarations and defines accross read_verilog calls	2016-11-15 12:42:43 +01:00
Clifford Wolf	2874914bcb	Fixed anonymous genblock object names	2016-11-04 07:46:30 +01:00
Clifford Wolf	56e2bb88ae	Some fixes in handling of signed arrays	2016-11-01 23:17:43 +01:00
Clifford Wolf	aa72262330	Added avail params to ilang format, check module params in 'hierarchy -check'	2016-10-22 11:05:49 +02:00
Clifford Wolf	042b67f024	No limit for length of lines in BLIF front-end	2016-10-19 12:44:58 +02:00
Clifford Wolf	bdc316db50	Added $anyseq cell type	2016-10-14 15:24:03 +02:00
Clifford Wolf	53655d173b	Added $global_clock verilog syntax support for creating $ff cells	2016-10-14 12:33:56 +02:00
Clifford Wolf	8ebba8a35f	Added $ff and $_FF_ cell types	2016-10-12 01:18:39 +02:00
Clifford Wolf	8f5bf6de32	Added liberty parser support for types within cell decls	2016-09-23 13:53:23 +02:00
Clifford Wolf	aaa99c35bd	Added $past, $stable, $rose, $fell SVA functions	2016-09-19 01:30:07 +02:00
Clifford Wolf	13a03b84d4	Added support for bus interfaces to "read_liberty -lib"	2016-09-18 18:48:59 +02:00
Clifford Wolf	ab18e9df7c	Added assertpmux	2016-09-07 00:28:01 +02:00
Clifford Wolf	d55a93b39f	Bugfix in parsing of BLIF latch init values	2016-09-06 17:35:06 +02:00
Clifford Wolf	97583ab729	Avoid creation of bogus initial blocks for assert/assume in always @*	2016-09-06 17:34:42 +02:00
Clifford Wolf	aa25a4cec6	Added $anyconst support to yosys-smtbmc	2016-08-30 19:27:42 +02:00
Clifford Wolf	6f41e5277d	Removed $aconst cell type	2016-08-30 19:09:56 +02:00
Clifford Wolf	eae390ae17	Removed $predict again	2016-08-28 21:35:33 +02:00
Clifford Wolf	1276c87a56	Added read_verilog -norestrict -assume-asserts	2016-08-26 23:35:27 +02:00
Clifford Wolf	4be4969bae	Improved verilog parser errors	2016-08-25 11:44:37 +02:00
Clifford Wolf	cd18235f30	Added SV "restrict" keyword	2016-08-24 15:30:08 +02:00
Clifford Wolf	450f6f59b4	Fixed bug with memories that do not have a down-to-zero data width	2016-08-22 14:27:46 +02:00
Clifford Wolf	82a4a0230f	Another bugfix in mem2reg code	2016-08-21 13:23:58 +02:00
Clifford Wolf	dbdd8927e7	Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog()	2016-08-21 13:18:09 +02:00
Clifford Wolf	fe9315b7a1	Fixed finish_addr handling in $readmemh/$readmemb	2016-08-20 13:47:46 +02:00
Clifford Wolf	f6629b9c29	Optimize memory address port width in wreduce and memory_collect, not verilog front-end	2016-08-19 18:38:25 +02:00
Clifford Wolf	e9fe57c75e	Only allow posedge/negedge with 1 bit wide signals	2016-08-10 19:32:11 +02:00
Clifford Wolf	7f755dec75	Fixed bug in parsing real constants	2016-08-06 13:16:23 +02:00
Clifford Wolf	4056312987	Added $anyconst and $aconst	2016-07-27 15:41:22 +02:00
Clifford Wolf	a7b0769623	Added "read_verilog -dump_rtlil"	2016-07-27 15:40:17 +02:00
Clifford Wolf	5b944ef11b	Fixed a verilog parser memory leak	2016-07-25 16:37:58 +02:00
Clifford Wolf	7a67add95d	Fixed parsing of empty positional cell ports	2016-07-25 12:48:03 +02:00
Clifford Wolf	9aae1d1e8f	No tristate warning message for "read_verilog -lib"	2016-07-23 11:56:53 +02:00
Clifford Wolf	7fef5ff104	Using $initstate in "initial assume" and "initial assert"	2016-07-21 14:37:28 +02:00
Clifford Wolf	5c166e76e5	Added $initstate cell type and vlog function	2016-07-21 14:23:22 +02:00
Clifford Wolf	d7763634b6	After reading the SV spec, using non-standard predict() instead of expect()	2016-07-21 13:34:33 +02:00
Clifford Wolf	721f1f5ecf	Added basic support for $expect cells	2016-07-13 16:56:17 +02:00
Clifford Wolf	9a101dc1f7	Fixed mem assignment in left-hand-side concatenation	2016-07-08 14:31:06 +02:00
Ruben Undheim	545bcb37e8	Allow defining input ports as "input logic" in SystemVerilog	2016-06-20 20:16:37 +02:00
Clifford Wolf	9bca8ccd40	Merge branch 'sv_packages' of https://github.com/rubund/yosys	2016-06-19 15:48:40 +02:00
Ruben Undheim	a8200a773f	A few modifications after pull request comments ... - Renamed Design::packages to Design::verilog_packages - No need to include ast.h in rtlil.h	2016-06-18 14:23:38 +02:00
Clifford Wolf	9e28290b0f	Added "read_blif -sop"	2016-06-18 12:33:13 +02:00
Ruben Undheim	178ff3e7f6	Added support for SystemVerilog packages with localparam definitions	2016-06-18 10:53:55 +02:00
Clifford Wolf	52bb1b968d	Added $sop cell type and "abc -sop"	2016-06-17 13:50:09 +02:00
Clifford Wolf	766032c5f8	Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}	2016-05-27 17:55:03 +02:00