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After reading the SV spec, using non-standard predict() instead of expect()

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This commit is contained in:
Clifford Wolf 2016-07-21 13:34:33 +02:00
parent 721f1f5ecf
commit d7763634b6
16 changed files with 28 additions and 32 deletions
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2
frontends/ast/ast.cc
View file

@ -82,7 +82,7 @@ std::string AST::type2str(AstNodeType type)
X(AST_PREFIX)
X(AST_ASSERT)
X(AST_ASSUME)
X(AST_EXPECT)
X(AST_PREDICT)
X(AST_FCALL)
X(AST_TO_BITS)
X(AST_TO_SIGNED)

2
frontends/ast/ast.h
View file

@ -65,7 +65,7 @@ namespace AST
AST_PREFIX,
AST_ASSERT,
AST_ASSUME,
AST_EXPECT,
AST_PREDICT,
AST_FCALL,
AST_TO_BITS,

4
frontends/ast/genrtlil.cc
View file

@ -1296,11 +1296,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// generate $assert cells
case AST_ASSERT:
case AST_ASSUME:
case AST_EXPECT:
case AST_PREDICT:
{
const char *celltype = "$assert";
if (type == AST_ASSUME) celltype = "$assume";
if (type == AST_EXPECT) celltype = "$expect";
if (type == AST_PREDICT) celltype = "$predict";
log_assert(children.size() == 2);

4
frontends/ast/simplify.cc
View file

@ -1348,7 +1348,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
}
skip_dynamic_range_lvalue_expansion:;
if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_EXPECT) && current_block != NULL)
if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_PREDICT) && current_block != NULL)
{
std::stringstream sstr;
sstr << "$formal$" << filename << ":" << linenum << "$" << (autoidx++);
@ -1405,7 +1405,7 @@ skip_dynamic_range_lvalue_expansion:;
goto apply_newNode;
}
if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_EXPECT) && children.size() == 1)
if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_PREDICT) && children.size() == 1)
{
children.push_back(mkconst_int(1, false, 1));
did_something = true;

6
frontends/verilog/verilog_lexer.l
View file

@ -63,6 +63,10 @@ YOSYS_NAMESPACE_END
frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); \
return TOK_ID;
#define NON_KEYWORD() \
frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); \
return TOK_ID;
#define YY_INPUT(buf,result,max_size) \
result = readsome(*VERILOG_FRONTEND::lexin, buf, max_size)
@ -173,7 +177,7 @@ YOSYS_NAMESPACE_END
"assert" { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); }
"assume" { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
"expect" { if (formal_mode) return TOK_EXPECT; SV_KEYWORD(TOK_EXPECT); }
"predict" { if (formal_mode) return TOK_PREDICT; NON_KEYWORD(); }
"property" { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); }
"logic" { SV_KEYWORD(TOK_REG); }
"bit" { SV_KEYWORD(TOK_REG); }

10
frontends/verilog/verilog_parser.y
View file

@ -113,7 +113,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
%token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
%token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_ASSUME
%token TOK_EXPECT TOK_PROPERTY
%token TOK_PREDICT TOK_PROPERTY
%type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
@ -967,8 +967,8 @@ assert:
TOK_ASSUME '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $3));
} |
TOK_EXPECT '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_EXPECT, $3));
TOK_PREDICT '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_PREDICT, $3));
};
assert_property:
@ -978,8 +978,8 @@ assert_property:
TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4));
} |
TOK_EXPECT TOK_PROPERTY '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_EXPECT, $4));
TOK_PREDICT TOK_PROPERTY '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_PREDICT, $4));
};
simple_behavioral_stmt: