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Added support for SystemVerilog packages with localparam definitions

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This commit is contained in:
Ruben Undheim 2016-06-18 10:24:21 +02:00
parent 3380281e15
commit 178ff3e7f6
7 changed files with 53 additions and 1 deletions
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12
frontends/ast/ast.cc
View file

@ -151,6 +151,7 @@ std::string AST::type2str(AstNodeType type)
X(AST_POSEDGE)
X(AST_NEGEDGE)
X(AST_EDGE)
X(AST_PACKAGE)
#undef X
default:
log_abort();
@ -996,6 +997,14 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
for (auto n : global_decls)
(*it)->children.push_back(n->clone());
for (auto n : design->packages){
for (auto o : n->children) {
AstNode *cloned_node = o->clone();
cloned_node->str = n->str + std::string("::") + cloned_node->str.substr(1);
(*it)->children.push_back(cloned_node);
}
}
if (flag_icells && (*it)->str.substr(0, 2) == "\\$")
(*it)->str = (*it)->str.substr(1);
@ -1013,6 +1022,9 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
design->add(process_module(*it, defer));
}
else if ((*it)->type == AST_PACKAGE){
design->packages.push_back((*it)->clone());
}
else
global_decls.push_back(*it);
}

4
frontends/ast/ast.h
View file

@ -137,7 +137,9 @@ namespace AST
AST_POSEDGE,
AST_NEGEDGE,
AST_EDGE
AST_EDGE,
AST_PACKAGE
};
// convert an node type to a string (e.g. for debug output)

1
frontends/ast/genrtlil.cc
View file

@ -806,6 +806,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_GENBLOCK:
case AST_GENIF:
case AST_GENCASE:
case AST_PACKAGE:
break;
// remember the parameter, needed for example in techmap

4
frontends/verilog/verilog_lexer.l
View file

@ -141,6 +141,8 @@ YOSYS_NAMESPACE_END
"endfunction" { return TOK_ENDFUNCTION; }
"task" { return TOK_TASK; }
"endtask" { return TOK_ENDTASK; }
"package" { SV_KEYWORD(TOK_PACKAGE); }
"endpackage" { SV_KEYWORD(TOK_ENDPACKAGE); }
"parameter" { return TOK_PARAMETER; }
"localparam" { return TOK_LOCALPARAM; }
"defparam" { return TOK_DEFPARAM; }
@ -351,6 +353,8 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
"<<<" { return OP_SSHL; }
">>>" { return OP_SSHR; }
"::" { SV_KEYWORD(TOK_PACKAGESEP); }
"+:" { return TOK_POS_INDEXED; }
"-:" { return TOK_NEG_INDEXED; }

29
frontends/verilog/verilog_parser.y
View file

@ -102,6 +102,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
%token <string> TOK_STRING TOK_ID TOK_CONST TOK_REALVAL TOK_PRIMITIVE
%token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
%token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
%token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG
%token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
%token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
@ -155,6 +156,7 @@ design:
task_func_decl design |
param_decl design |
localparam_decl design |
package design |
/* empty */;
attr:
@ -212,6 +214,14 @@ hierarchical_id:
TOK_ID {
$$ = $1;
} |
hierarchical_id TOK_PACKAGESEP TOK_ID {
if ($3->substr(0, 1) == "\\")
*$1 += "::" + $3->substr(1);
else
*$1 += "::" + *$3;
delete $3;
$$ = $1;
} |
hierarchical_id '.' TOK_ID {
if ($3->substr(0, 1) == "\\")
*$1 += "." + $3->substr(1);
@ -311,6 +321,25 @@ module_arg:
do_not_require_port_stubs = true;
};
package:
attr TOK_PACKAGE TOK_ID {
AstNode *mod = new AstNode(AST_PACKAGE);
ast_stack.back()->children.push_back(mod);
ast_stack.push_back(mod);
current_ast_mod = mod;
mod->str = *$3;
append_attr(mod, $1);
} ';' package_body TOK_ENDPACKAGE {
ast_stack.pop_back();
current_ast_mod = NULL;
};
package_body:
package_body package_body_stmt |;
package_body_stmt:
localparam_decl;
non_opt_delay:
'#' '(' expr ')' { delete $3; } |
'#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };