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Added basic support for $expect cells

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This commit is contained in:
Clifford Wolf 2016-07-13 16:56:17 +02:00
parent b3155af5f6
commit 721f1f5ecf
16 changed files with 82 additions and 19 deletions
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1
frontends/ast/ast.cc
View file

@ -82,6 +82,7 @@ std::string AST::type2str(AstNodeType type)
X(AST_PREFIX)
X(AST_ASSERT)
X(AST_ASSUME)
X(AST_EXPECT)
X(AST_FCALL)
X(AST_TO_BITS)
X(AST_TO_SIGNED)

1
frontends/ast/ast.h
View file

@ -65,6 +65,7 @@ namespace AST
AST_PREFIX,
AST_ASSERT,
AST_ASSUME,
AST_EXPECT,
AST_FCALL,
AST_TO_BITS,

9
frontends/ast/genrtlil.cc
View file

@ -1296,7 +1296,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// generate $assert cells
case AST_ASSERT:
case AST_ASSUME:
case AST_EXPECT:
{
const char *celltype = "$assert";
if (type == AST_ASSUME) celltype = "$assume";
if (type == AST_EXPECT) celltype = "$expect";
log_assert(children.size() == 2);
RTLIL::SigSpec check = children[0]->genRTLIL();
@ -1308,9 +1313,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
en = current_module->ReduceBool(NEW_ID, en);
std::stringstream sstr;
sstr << (type == AST_ASSERT ? "$assert$" : "$assume$") << filename << ":" << linenum << "$" << (autoidx++);
sstr << celltype << "$" << filename << ":" << linenum << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_ASSERT ? "$assert" : "$assume");
RTLIL::Cell *cell = current_module->addCell(sstr.str(), celltype);
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
for (auto &attr : attributes) {

12
frontends/ast/simplify.cc
View file

@ -1348,10 +1348,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
}
skip_dynamic_range_lvalue_expansion:;
if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME) && current_block != NULL)
if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_EXPECT) && current_block != NULL)
{
std::stringstream sstr;
sstr << "$assert$" << filename << ":" << linenum << "$" << (autoidx++);
sstr << "$formal$" << filename << ":" << linenum << "$" << (autoidx++);
std::string id_check = sstr.str() + "_CHECK", id_en = sstr.str() + "_EN";
AstNode *wire_check = new AstNode(AST_WIRE);
@ -1363,8 +1363,10 @@ skip_dynamic_range_lvalue_expansion:;
AstNode *wire_en = new AstNode(AST_WIRE);
wire_en->str = id_en;
current_ast_mod->children.push_back(wire_en);
current_ast_mod->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1)))));
current_ast_mod->children.back()->children[0]->children[0]->children[0]->str = id_en;
if (current_always == nullptr || current_always->type != AST_INITIAL) {
current_ast_mod->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1)))));
current_ast_mod->children.back()->children[0]->children[0]->children[0]->str = id_en;
}
current_scope[wire_en->str] = wire_en;
while (wire_en->simplify(true, false, false, 1, -1, false, false)) { }
@ -1403,7 +1405,7 @@ skip_dynamic_range_lvalue_expansion:;
goto apply_newNode;
}
if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME) && children.size() == 1)
if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_EXPECT) && children.size() == 1)
{
children.push_back(mkconst_int(1, false, 1));
did_something = true;

1
frontends/verilog/verilog_lexer.l
View file

@ -173,6 +173,7 @@ YOSYS_NAMESPACE_END
"assert" { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); }
"assume" { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
"expect" { if (formal_mode) return TOK_EXPECT; SV_KEYWORD(TOK_EXPECT); }
"property" { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); }
"logic" { SV_KEYWORD(TOK_REG); }
"bit" { SV_KEYWORD(TOK_REG); }

9
frontends/verilog/verilog_parser.y
View file

@ -112,7 +112,8 @@ static void free_attr(std::map<std::string, AstNode*> *al)
%token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
%token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
%token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_ASSUME TOK_PROPERTY
%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_ASSUME
%token TOK_EXPECT TOK_PROPERTY
%type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
@ -965,6 +966,9 @@ assert:
} |
TOK_ASSUME '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $3));
} |
TOK_EXPECT '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_EXPECT, $3));
};
assert_property:
@ -973,6 +977,9 @@ assert_property:
} |
TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4));
} |
TOK_EXPECT TOK_PROPERTY '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_EXPECT, $4));
};
simple_behavioral_stmt: