mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-11-04 05:19:11 +00:00 
			
		
		
		
	Bugfix in parsing of BLIF latch init values
This commit is contained in:
		
							parent
							
								
									97583ab729
								
							
						
					
					
						commit
						d55a93b39f
					
				
					 1 changed files with 1 additions and 1 deletions
				
			
		| 
						 | 
				
			
			@ -241,7 +241,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 | 
			
		|||
				}
 | 
			
		||||
 | 
			
		||||
				if (init != nullptr && (init[0] == '0' || init[0] == '1'))
 | 
			
		||||
					blif_wire(d)->attributes["\\init"] = Const(init[0] == '1' ? 1 : 0, 1);
 | 
			
		||||
					blif_wire(q)->attributes["\\init"] = Const(init[0] == '1' ? 1 : 0, 1);
 | 
			
		||||
 | 
			
		||||
				if (clock == nullptr)
 | 
			
		||||
					goto no_latch_clock;
 | 
			
		||||
| 
						 | 
				
			
			
 | 
			
		|||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue