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Removed $predict again

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This commit is contained in:
Clifford Wolf 2016-08-28 21:35:33 +02:00
parent 66582964bc
commit eae390ae17
15 changed files with 7 additions and 38 deletions
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1
frontends/ast/ast.cc
View file

@ -83,7 +83,6 @@ std::string AST::type2str(AstNodeType type)
X(AST_PREFIX)
X(AST_ASSERT)
X(AST_ASSUME)
X(AST_PREDICT)
X(AST_FCALL)
X(AST_TO_BITS)
X(AST_TO_SIGNED)

1
frontends/ast/ast.h
View file

@ -65,7 +65,6 @@ namespace AST
AST_PREFIX,
AST_ASSERT,
AST_ASSUME,
AST_PREDICT,
AST_FCALL,
AST_TO_BITS,

2
frontends/ast/genrtlil.cc
View file

@ -1317,11 +1317,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// generate $assert cells
case AST_ASSERT:
case AST_ASSUME:
case AST_PREDICT:
{
const char *celltype = "$assert";
if (type == AST_ASSUME) celltype = "$assume";
if (type == AST_PREDICT) celltype = "$predict";
log_assert(children.size() == 2);

4
frontends/ast/simplify.cc
View file

@ -1352,7 +1352,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
}
skip_dynamic_range_lvalue_expansion:;
if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_PREDICT) && current_block != NULL)
if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME) && current_block != NULL)
{
std::stringstream sstr;
sstr << "$formal$" << filename << ":" << linenum << "$" << (autoidx++);
@ -1414,7 +1414,7 @@ skip_dynamic_range_lvalue_expansion:;
goto apply_newNode;
}
if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_PREDICT) && children.size() == 1)
if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME) && children.size() == 1)
{
children.push_back(mkconst_int(1, false, 1));
did_something = true;

1
frontends/verilog/verilog_lexer.l
View file

@ -178,7 +178,6 @@ YOSYS_NAMESPACE_END
"assert" { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); }
"assume" { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
"restrict" { if (formal_mode) return TOK_RESTRICT; SV_KEYWORD(TOK_RESTRICT); }
"predict" { if (formal_mode) return TOK_PREDICT; NON_KEYWORD(); }
"property" { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); }
"logic" { SV_KEYWORD(TOK_REG); }
"bit" { SV_KEYWORD(TOK_REG); }

8
frontends/verilog/verilog_parser.y
View file

@ -114,7 +114,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
%token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
%token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_ASSUME
%token TOK_RESTRICT TOK_PREDICT TOK_PROPERTY
%token TOK_RESTRICT TOK_PROPERTY
%type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
@ -1006,9 +1006,6 @@ assert:
delete $3;
else
ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $3));
} |
TOK_PREDICT '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_PREDICT, $3));
};
assert_property:
@ -1023,9 +1020,6 @@ assert_property:
delete $4;
else
ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4));
} |
TOK_PREDICT TOK_PROPERTY '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_PREDICT, $4));
};
simple_behavioral_stmt: