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438 commits

Author SHA1 Message Date
Natalia
b6715cf74d Simplify regex to be more permissive
Make the regex less strict about exact whitespace and format. Just look
for a number followed by 'wires' or 'ports' anywhere on the line.
2026-01-14 13:59:26 -08:00
Natalia
1b592c7f8d Fix TCL regex to use POSIX character classes
TCL doesn't support \d and \s escape sequences in regexes. Use [0-9] and
[ \t] instead to match digits and whitespace.
2026-01-14 13:21:16 -08:00
Natalia
a4774cac02 Fix test regex to match upstream stat output format
The test was using regexes that matched Silimate's modified stat output
format ('Number of wires:  <count>'), but upstream yosys uses a different
format (' <count> <area>  wires'). Update the regex to match the upstream
format.
2026-01-14 12:55:18 -08:00
Natalia
6503ad91c9 splitnets: add -ports_only and -top_only options
Add two new options to the splitnets pass:

- `-ports_only`: Split only module ports, not internal signals. This is
  useful when you want to split ports for interface compatibility while
  keeping internal signals as multi-bit wires for better readability.

- `-top_only`: Apply splitting only at the top module level, not in
  submodules. This is helpful for hierarchical designs where you need
  split signals only at the top-level interface.

These options can be combined with existing flags:
- `splitnets -ports_only`: Split all ports in all modules
- `splitnets -ports_only -top_only`: Split ports only in top module
- `splitnets -ports -top_only`: Split both ports and nets only in top

Add comprehensive tests that verify wire/port counts for all flag
combinations using a hierarchical design.
2026-01-14 12:01:22 -08:00
Robert O'Callahan
914e14946d Implement design_equal command 2025-12-21 21:47:40 +00:00
Krystine Sherwin
a8e8746fc0
tests: Tidy up bug3515
Add base case where mapping is possible for sanity checking.
2025-11-25 07:35:19 +13:00
Krystine Sherwin
ba31a02578
tests: Add bug3515 2025-11-25 07:04:34 +13:00
Anhijkt
b08195a9cf typo 2025-11-14 13:34:58 +02:00
Anhijkt
a75b999f13 fsm_detect: fix test 2025-11-14 13:25:51 +02:00
Anhijkt
7d10a72490 fsm_detect: add adff detection 2025-11-06 23:29:47 +02:00
Martin Povišer
5fa7feccd3 timeest: Add top ports launching/sampling 2025-11-03 14:21:28 +01:00
Mohamed Gaber
e86797f029
plugins: add search path
This uses the environment variable `YOSYS_PLUGIN_PATH` to provide multiple colon-delimited search paths for native plugins in a similar manner to `PATH` for executables and `PYTHONPATH` for Python modules.

This addresses https://github.com/YosysHQ/yosys/issues/2545, allowing Yosys to be better packaged in non-FHS environments such as Nix.
2025-10-15 14:13:25 +03:00
Emil J. Tywoniak
c46df9ffdc box_derive: rename -apply to -apply_derived_type 2025-10-13 17:24:32 +02:00
Emil J. Tywoniak
d7cea2c35c box_derive: add -apply 2025-10-13 17:24:32 +02:00
Jannis Harder
86fb2f16f7 bufnorm: Refactor and fix incremental bufNormalize
This fixes some edge cases the previous version didn't handle properly
by simplifying the logic of determining directly driven wires and
representatives to use as buffer inputs.
2025-09-29 08:21:28 +02:00
KrystalDelusion
7ebd972165
Merge pull request #5277 from YosysHQ/krys/fix_4983_alt
autoname: Avoid integer overflow
2025-09-26 14:11:20 +12:00
Krystine Sherwin
941ba3b745
autoname.ys: Extra check for rename order
Disabling comparison with best score will cause this check to fail.  Preferred names will not be possible if $name2 has not yet been renamed.
2025-09-26 11:36:23 +12:00
Krystine Sherwin
fef6bdae6c
autoname.cc: Return number of renames
Was previously the number of proposed renames, but since renames can be skipped this causes the final count to differ from the number of actually renamed objects.
Check counts in `tests/various/autoname.ys`.
2025-09-26 11:05:50 +12:00
KrystalDelusion
d4071b63f7
Merge pull request #5268 from YosysHQ/krys/cutpoint_inout
Track wire drivers in cutpoint
2025-09-24 04:14:19 +12:00
Jannis Harder
d88d6fce87 kernel: Rewrite bufNormalize
This is a complete rewrite of the RTLIL-kernel-side bufnorm code. This
is done to support inout ports and undirected connections as well as to
allow removal of cells while in bufnorm mode.

This doesn't yet update the (experimental) `bufnorm` pass, so to
manually test the new kernel functionality, it is important to only use
`bufnorm -update` and `bufnorm -reset` which rely entirely on the kernel
functionality. Other modes of the `bufnorm` pass may still fail in the
presence of inout ports or undirected connections.
2025-09-17 13:56:46 +02:00
George Rennie
8fb3f88842 tests: remove -seq 1 from sat with -tempinduct where possible
* When used with -tempinduct mode, -seq <N> causes assertions to be
  ignored in the first N steps. While this has uses for reset modelling,
  for these test cases it is unnecessary and could lead to failures
  slipping through uncaught
2025-09-08 18:04:32 +02:00
Krystine Sherwin
bc77b6213b autoname: Fix selection arg 2025-09-05 00:15:26 +02:00
Krystine Sherwin
f45255f5a2 tests: More autoname tests 2025-09-05 00:15:26 +02:00
Jannis Harder
7c409e2d5a
Merge pull request #5285 from jix/abstract_initstates
abstract: Add -initstates option
2025-08-18 15:39:09 +02:00
KrystalDelusion
6d55ca204b
Merge pull request #5281 from suisseWalter/add_parameterised_cells_stat
STAT: Add parameterised cells
2025-08-18 09:21:45 +12:00
clemens
9278bed853 removed copyright notice on lib file.
Should be covered by the yosys license not  anything else.
2025-08-16 09:40:03 +02:00
clemens
73d1177665 testcases
one testcase for single parameter cells.
one testcase for double parameter cells.
2025-08-16 09:40:03 +02:00
clemens
d8fb4da437 updated testcase 2025-08-16 09:32:08 +02:00
Krystine Sherwin
ec18d1aede
rename.cc: Fixup ports after -unescape 2025-08-15 10:48:32 +12:00
clemens
71307b4a51 add Testcases
Fix existing testcases
Fix edgecase where modules where counted as cells.
2025-08-13 14:46:01 +02:00
Jannis Harder
77089a8d03 rename: add -move-to-cell option in -wire mode 2025-08-13 11:11:52 +02:00
Jannis Harder
1f876f3a22 abstract: Add -initstates option 2025-08-12 15:37:12 +02:00
KrystalDelusion
1ae82d7b9d
Merge pull request #5233 from YosysHQ/krys/equiv_assume
Assumptions for equiv_*
2025-08-09 10:39:04 +12:00
Krystine Sherwin
af7d1d3f4f
cutpoint_blackbox.ys: Extra edge case 2025-08-06 18:11:35 +12:00
Krystine Sherwin
1bf9530fcc
cutpoint_blackbox.ys: Add verific-style unknown module 2025-08-06 16:51:14 +12:00
Krystine Sherwin
f9e8127e2b
tests: Add equiv_induct to equiv_assume.ys 2025-08-06 15:13:04 +12:00
Robert O'Callahan
8b75c06141 Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
N. Engelhardt
d009bcc9b6
Merge pull request #5198 from YosysHQ/nak/lcov 2025-07-17 11:57:58 +02:00
N. Engelhardt
fb6974dcd7 print summary of line coverage to log 2025-07-16 13:40:07 +02:00
Krystine Sherwin
5ec189a2f5
Tests: Extra equiv_assume tests 2025-07-16 21:06:04 +12:00
Krystine Sherwin
d30f934d0d
equiv_simple: Add -set-assumes option
Based on existing code for input cone and the `sat` handling of `-set-assumes`.
Update `equiv_assume.ys` to use `-set-assumes` option.
2025-07-16 21:04:41 +12:00
Krystine Sherwin
a57c593c41
tests: Add equiv_assume.ys 2025-07-16 15:32:47 +12:00
N. Engelhardt
02323295b0
Merge pull request #5179 from YosysHQ/krys/assert2cover 2025-07-10 14:53:22 +02:00
N. Engelhardt
8a4f465143 update test to use suggested selection for assertions 2025-07-01 11:46:27 +02:00
N. Engelhardt
ef3f541501 add linecoverage command to generate lcov report from selection 2025-06-26 13:21:53 +02:00
Emil J. Tywoniak
2b659626a3 rename: add -unescape 2025-06-24 12:33:33 +02:00
Krystine Sherwin
45131f4425
chformal: Add -assert2cover option
Also add to chformal tests.
2025-06-14 10:54:23 +12:00
Emil J. Tywoniak
239c265093 splitnets: handle single-bit vectors consistently 2025-06-05 10:58:06 +02:00
Krystine Sherwin
7c89355b70
cutpoint: Re-add whole module optimization
Also add a test script for it.
2025-05-06 09:57:34 +12:00
N. Engelhardt
84c49e1f33
Merge pull request #5041 from jix/declockgate-v2 2025-04-28 13:31:11 +00:00