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tests: Add equiv_assume.ys

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Krystine Sherwin 2025-07-16 15:32:47 +12:00
parent af0b263557
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@ -0,0 +1,26 @@
read_verilog -sv <<EOT
module gold (input D, output Q);
assign Q = '0;
endmodule
module gate (input D, output Q);
assume property (D == '0);
assign Q = D;
endmodule
EOT
chformal -lower
async2sync
design -stash input
# using $assert cells in sat verifies
design -load input
equiv_make -make_assert gold gate equiv
prep -top equiv
sat -set-assumes -prove-asserts -verify
# so should $equiv
design -load input
equiv_make gold gate equiv
equiv_simple equiv
equiv_status -assert equiv