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rename.cc: Fixup ports after -unescape

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Krystine Sherwin 2025-08-15 10:48:32 +12:00
parent 195d3ef940
commit ec18d1aede
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2
passes/cmds/rename.cc
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@ -598,6 +598,8 @@ struct RenamePass : public Pass {
for (auto &it : new_cell_names)
module->rename(it.first, it.second);
module->fixup_ports();
}
}
else

15
tests/various/rename_unescape.ys
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@ -39,3 +39,18 @@ select -assert-count 1 w:d__1
select -assert-count 1 w:_e
select -assert-count 1 w:wire_
select -assert-count 1 w:$add$<<EOF:*$1_Y
# Ports are updated during rename
design -reset
read_verilog << EOT
module top(output \$e );
submod \a$ (\$e );
endmodule
module submod(output \a[0] );
assign \a[0] = 0;
endmodule
EOT
rename -unescape
check