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cutpoint_blackbox.ys: Extra edge case
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@ -87,3 +87,27 @@ end
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EOT
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cutpoint -blackbox
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check -assert
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# also concatenated signals, and signals between two inout ports
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design -load hier
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delete top =bb
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read_verilog << EOT
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module top(input [1:0] a, b, output [1:0] o);
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wire [1:0] c, d, e;
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bb #(.SOME_PARAM(1)) bb1 (.a ({a[0], e[1]}), .b (b), .o (c));
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bb #(.SOME_PARAM(2)) bb2 (.a ({c[1], a[0]}), .b (c), .o (d));
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wb wb1 (.a (a), .b (b), .o (e));
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some_mod some_inst (.a (c), .b (d), .c (e), .o (o));
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endmodule
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EOT
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read_rtlil << EOT
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attribute \blackbox 1
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module \bb
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parameter \SOME_PARAM 0
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wire inout 3 width 2 \o
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wire inout 2 width 2 \b
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wire inout 1 width 2 \a
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end
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EOT
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cutpoint -blackbox
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check -assert
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