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Merge pull request #5281 from suisseWalter/add_parameterised_cells_stat

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STAT: Add parameterised cells
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KrystalDelusion 2025-08-18 09:21:45 +12:00 • committed by GitHub
commit 6d55ca204b
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6 changed files with 963 additions and 149 deletions
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837
passes/cmds/stat.cc
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5
tests/various/stat.ys
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@ -11,6 +11,8 @@ end
EOT
logger -expect log "Chip area for module '\\top': 9.072000" 1
logger -expect-no-warnings
logger -expect log " 1 9.072 cells" 1
logger -expect log " 1 9.072 sg13g2_and2_1" 1
stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz
@ -70,5 +72,8 @@ end
EOT
logger -expect log "Chip area for top module '\\top': 112.492800" 1
logger -expect log "of which used for sequential elements: 94.348800" 1
logger -expect log "2 18.144 cells" 1
logger -expect log "4 112.493 cells" 1
logger -expect log "2 94.349 sg13g2_dfrbp_1" 1
logger -expect-no-warnings
stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz -top \top

25
tests/various/stat_area_by_width.lib Normal file
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62
tests/various/stat_hierarchy.ys Normal file
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@ -0,0 +1,62 @@
read_rtlil << EOT
module \top
wire input 1 \A
wire output 2 \Y
wire output 3 \N
cell \sg13g2_and2_1 \sub1
connect \A \A
connect \B 1'0
connect \Y \Y
end
cell \child \sequential
connect \A \A
connect \B 1'0
connect \R 1'0
connect \Y \Y
connect \N \N
end
cell \child \sequential1
connect \A \A
connect \B 1'0
connect \R 1'0
connect \Y \Y
connect \N \N
end
cell \sg13g2_and2_1 \sub2
connect \A \A
connect \B 1'0
connect \Y \Y
end
end
module \child
wire input 1 \A
wire input 2 \B
wire input 3 \R
wire output 4 \Y
wire output 5 \N
cell \sg13g2_dfrbp_1 \sequential_ff
connect \CLK \A
connect \D \B
connect \Q \Y
connect \Q_N \N
connect \RESET_B \R
end
end
EOT
logger -expect log "4 112.493 2 18.144 cells" 2
logger -expect log "2 18.144 2 18.144 sg13g2_and2_1" 2
logger -expect log "2 94.349 - - sg13g2_dfrbp_1" 2
logger -expect log "2 94.349 2 - submodules" 2
logger -expect-no-warnings
stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz -top \top -hierarchy

92
tests/various/stat_high_level.ys Normal file
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read_rtlil << EOT
module \top
wire input 1 \A
wire output 2 \Y
wire output 3 \N
cell $and \sub1
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \A
connect \B 1'0
connect \Y \Y
end
cell \child \sequential
connect \A \A
connect \B 1'0
connect \R 1'0
connect \Y \Y
connect \N \N
end
cell \child \sequential1
connect \A \A
connect \B 1'0
connect \R 1'0
connect \Y \Y
connect \N \N
end
cell $xor \sub2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \A
connect \B 1'0
connect \Y \Y
end
end
module \child
wire input 1 \A
wire input 2 \B
wire input 3 \R
wire output 4 \Y
wire output 5 \N
wire \Y1
wire \Y2
cell \sg13g2_dfrbp_1 \sequential_ff
connect \CLK \A
connect \D \Y2
connect \Q \Y
connect \Q_N \N
connect \RESET_B \R
end
cell $xor \sub2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \B
connect \B 1'0
connect \Y \Y1
end
cell $reduce_xor \sub3
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \Y_WIDTH 1
connect \A 10'0000000000
connect \Y \Y2
end
end
EOT
logger -expect log "Chip area for top module '\\top': 66.000000" 1
logger -expect log "3 30.5 3 30.5 cells" 1
logger -expect log "2 51 - - \$reduce_xor" 2
logger -expect log "8 66 2 5 cells" 2
logger -expect-no-warnings
stat -liberty ./stat_area_by_width.lib -top \top -hierarchy

91
tests/various/stat_high_level2.ys Normal file
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@ -0,0 +1,91 @@
read_rtlil << EOT
module \top
wire input 1 \A
wire output 2 \Y
wire output 3 \N
cell $and \sub1
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \A
connect \B 1'0
connect \Y \Y
end
cell \child \sequential
connect \A \A
connect \B 1'0
connect \R 1'0
connect \Y \Y
connect \N \N
end
cell \child \sequential1
connect \A \A
connect \B 1'0
connect \R 1'0
connect \Y \Y
connect \N \N
end
cell $xor \sub2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \A
connect \B 1'0
connect \Y \Y
end
end
module \child
wire input 1 \A
wire input 2 \B
wire input 3 \R
wire output 4 \Y
wire output 5 \N
wire \Y1
wire \Y2
wire width 2 \A2
cell \sg13g2_dfrbp_1 \sequential_ff
connect \CLK \A
connect \D \Y2
connect \Q \Y
connect \Q_N \N
connect \RESET_B \R
end
cell $bmux \bmux1
parameter \WIDTH 2
parameter \S_WIDTH 2
connect \A 8'00000000
connect \S 2'00
connect \Y \A2
end
cell $reduce_xor \sub3
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \Y_WIDTH 1
connect \A 10'0000000000
connect \Y \Y2
end
end
EOT
logger -expect log "Chip area for top module '\\top': 80.000000" 1
logger -expect log "1 12 1 12 \$bmux" 1
logger -expect log "3 37.5 3 37.5 cells" 1
logger -expect log "8 80 2 5 cells" 2
logger -expect-no-warnings
stat -liberty ./stat_area_by_width.lib -top \top -hierarchy